Riichiro Shirota
Distinguished Professor,IEEE Fellow
Job title Distinguished Professor
Name Riichiro Shirota
Office Tel No. 03-5712121 ext59422
Email rshirota@faculty.nctu.edu.tw
Professor Profile 1) guest professor of Beijin Institute of Technology-- probably even nowvalid.2) Key contributor of the NAND Flash Memory technology3) He used to be the chief specialist of research in Toshiba
Research expertise 1.Research of device & design of Nonvolatile semiconductor memory IC2.Research of the system of Nonvolatile memory3.Research of 3-D structured Flash memory cell
0
Year Paper Title
2012 Ji.Ting.Liang, R.Shirota, et al, “Impacts of Edge Encroachments on Programming and Erasing Gate Currents of NAND-Type Flash Memory”, Submitted in IEEE transaction on Electron Devices, April, 2010.
2012 K.Imamiya, H.Nakamura, T.Himeno, T.Yamamura, T.Ikehashi, K.Takeuchi, K.Kanda, K.Hosono, T.Futatsuyama, K.Kawai, R.Shirota, N.Arai, F.Arai, K.Hatakeyama, H.Hazama, M.Saito, H.Meguro, K.Conley, K.Quanker, J.J.Chen, “A 125mm2 1-Gb NAND Flash Memory with 10-MByte/s Program Speed” in J. Solid-State Circuits, volume 37, pp.1493-1501, 2002.
 
2012 H.Toshihiko, K.Imamiya, R.Shirota, “256 Mbit NAND EEPROM with Shallow Trench Isolation Technology” in Toshiba Journal, in 1999
(see https://www.toshiba.co.jp/tech/review/1999/07/f04/index.htm).
 
2012 K.Imamiya, Y.Sugiura, H.Nakamura, T.Himeno, K.Takeuchi, T.Ikehashi, K.Kanda, K.Hosono, R.Shirota, S.Aritome, K.Shimizu, K.Hatakeyama, and K.Sakui, “A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology,” in IEEE J. Solid-State Circuits, pp. 1536-1543, Nov. 1999.
2012 T. Endoh, H. Iizuka, R. Shirota, and F. Masuoka, ”New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics”, IEICE Transactions on Electronics, vol. E80-C, No.10, pp. 1317-1323, October, 1997.
 
2012 T.Tanzawa, T.Tanaka, K.Takeuchi, R.Shirota, S.Aritome, H.Watanabe, G.Hemink, K.Shimizu, S.Sato, Y.Takeuchi, and K.Ohuchi, “A compact on-chip ECC for low cost Flash memories,” IEEE J. Solid-State Circuits, vol. 32, pp.662-669, May 1997.
2012 S.Aritome, Y.Takeuchi, S.Sato, H.Watanabe, K.Shimizu, G.J.Hemink, and R.Shirota, “A side-wall transfer-transistor cell (SWATT cell) for highly reliable multi-level NAND EEPROM’s,” IEEE Tran. Electron Devices, vol. 44, pp.145-152, Jan. 1997.
 
2012 H.Iizuka, T.Endoh, S.Aritome, R.Shirota, F.Masuoka, “A Novel Programming Method Using a Reverse Polarity Pulse in Flash EEPROMs”, in IEICE Transactions on Electronics, vol.E79-C, No.6, pp.832-835, June, 1996.
 
2012 T.Maruyama, R.Shiorta, “the low electric field conduction mechanism of silicon oxides-silicon nitride-silicon oxide inter poly-Si dielectrics.” J. Appl. Phys., vol. 78, no.6, Sep. 1995.
 
2012 T.Tanaka, Y.Tanaka, H.Nakamura, K.Sakui, R.Shirota, K.Ohuchi, and F.Masuoka, “A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3V-Only NAND Flash Memory,” IEEE J. Solid-State Circuits, vol.29, no.11, pp.1366-1373, Nov. 1994.
 
2012 G.Hemink, T.Endoh, R.Shirota, “Modeling of the Hole Current Caused by Fowler-Nordheim Tunneling.” J. Appl. Phys. Vol.33, no.1B, pp546-549, Jan. 1994.
 
2012 S.Aritome, R.Shirota, K.Sakui and F.Masuoka, “Data retention characteristics of Flash memory cells after write and erase cycling,” IEICE Trans. Electron., vol. E77-C, No.8, Aug. 1994.
 
2012 S.Aritome, I.Hatakeyama, T.Endoh, T.Yamaguchi, S.Shuto, H.Iizuka, T.Maruyama, H.Watanabe, G.J.Hemink, K.Sakui, T.Tanaka, M.Momodomi, and R.Shirota, “An advanced NAND-structured cell technology for reliable 3.3 V 64 Mb electrically erasable and programmable read only memories (EEPROMs),” Jpn. J. Appl. Phys. vol.33, no.1B, pp.524-528, Jan.1994.
 
2012 S.Aritome, R.Shirota, G.J.Hemink, T.Endoh, and F.Masuoka, “Reliability Issues of Flash Memory Cells,” Proceedings of the IEEE, vol.81, No.5, pp.776-788, May 1993.
 
2012 T.Endoh, R.Shirota, S.Aritome, F.Masuoka, “A Study of High-Performance NAND Structured EEPROMS, in IEICE Transactions on Electronics, Vol.E75-C, No.11, pp.1351-1357, Nov.1992.
 
2012 F.Masuoka, R.Shirota, and K.Sakui, “Invited Paper: Reviews and prospects of non-volatile semiconductor memories,” IEICE Trans., vol. E74, No.4, pp.868-874, April 1991.
 
2012 M.Momodomi, T.Tanaka, Y.Iwata, Y.Tanaka, H.Oodaira, Y.Itoh, R.Shirota, K.Ohuchi, and F.Masuoka, “A 4-Mbit NAND EEPROM with Tight Programmed Vt Distribution,” IEEE J. Solid-State Circuits, vol.26, no.4, pp.492-496, April 1991.
2012 T. ENDOH T, R.SHIROTA, M.MOMODOMI M, et al, “AN ACCURATE MODEL OF SUBBREAKDOWN DUE TO BAND-TO-BAND TUNNELING AND SOME APPLICATIONS,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 37, no. 1, pp. 290-296, Jan. 1990
 
2012 Y.Iwata, M.Momodomi, T.Tanaka, H.Oodaira, Y.Itoh, R.Nakayama, R.Kirisawa, S.Aritome, T.Endoh, R.Shirota, K.Ohuchi, and F.Masuoka, “A high-density NAND EEPROM with block-page programming for microcomputer applications,” IEEE J. Solid-State Circuits, vol.25, no.4, pp.417-424, April 1990.
 
2012 M.Momodomi, Y.Itoh, R.Shirota, Y.Iwata, R.Nakayama, R.Kirisawa, T.Tanaka, S.Aritome, T.Endoh, K.Ohuchi, and F.Masuoka, “An experimental 4-Mbit CMOS EEPROM with a NAND structured cell,” IEEE J. Solid-State Circuits, vol.24, no.10, pp.1238-1243, Oct.1989.
 
2012  Y. YOSHIDA, R.SHIROTA, K.AZUMI, "QUANTITATIVE MONITORING OF CHARGING-UP EMPLOYING EEPROM DEVICE ," JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 134, no. 8B, pp. C454-C454, AUG 1987.
 
2012 R.Shirota, K.Miyake, M.Itoh and K.Ymamda, “Dynamics of longitudinal component in orderd spin systems”, Progress of Theoretical Physics, Vol68, no.6, pp.1841-1853, 1982.
 
2012 R.Shirota, K.Miyake, M.Ito and K.Yamada,“Critical Dynamics of Longitudinal Component in Ordered Spin System,” Progress of Theortical .Physics, Vol.66, no.2, pp.721-724, Aug. 1981.
 
Year Paper Title
2010
Ø      IEDM
[1]  F.Masuoka, M.Momodomi, Y.Iwata, and R.Shirora, “New Ultra High Density EPROM and Flash EEPROM with NAND Structured Cell,” in IEDM Tech. Dig., pp.552-555, Dec. 1987.
[2]  M.Momodomi, R.Kirisawa, R.Nakayama, S.Aritome, T.Endoh, Y.Itoh, Y.Iwata, H.Oodaira, T.Tanaka, M.Chiba, R.Shirota, and F.Masuoka, “New device technologies for 5V-only 4Mb EE-PROM with NAND structure cell,” in IEDM Tech. Dig., pp.412-415, Dec. 1988.
[3]  R.Shirota, T.Endo, M.Momodomi, R.Nakayama, S.Inoue, R.Kirisawa, and F.Masuoka, “An accurate model of subbreakdown due to Band-to-Band tunneling and its application,” in IEDM Tech. Dig., pp.26-29, Dec. 1988.
[4]  T.Endo, R.Shirota, Y.Tanaka, R.Nakayama, R.Kirisawa, S.Aritome, and F.Masuoka, “New design technology for EEPROM memory cells with 10 million write/erase cycling endurance,” in IEDM Tech. Dig., pp.599-602, Dec. 1989.
[5]  R.Shirota, R.Nakayama, R.Kirisawa, M.Momodomi, K.Sakui, Y.Itoh, S.Aritome, T.Endoh, F.Hatori, and F.Masuoka, "A 2.3 m2 Memory Cell Structure for 16 Mb NAND EEPROM’s," in IEDM Tech. Dig., pp. 103-106, Dec. 1990.
[6]  S.Aritome, R.Shirota, R.Kirisawa, T.Endoh, R.Nakayama, K.Sakui, and F.Masuoka, “A reliable bi-polarity write/erase technology in Flash EEPROMs,” in IEDM Tech. Dig., pp.111-114, Dec. 1990.
[7]  R.Shirota, T.Yamaguchi, “A New Analytical Model for low Voltage Hot Electron Taking Auger Recombination as well as phonon Scattering Process into Account,” in IEDM Tech. Dig. pp.123-126. 1991.
[8]  S.Aritome, S.Satoh, T.Maruyama, H.Watanabe, S.Shuto, G.J.Hemink, R.Shirota, S.Watanabe, and F.Masuoka, "A 0.67m2 Self-Aligned Shallow Trench Isolation Cell (SA-STI-Cell) for 3V-only 256Mbit NAND EEPROM’s," in IEDM Tech. Dig., pp. 61-64, Dec. 1994.
[9]  S.Aritome, Y.Takeuchi, S.Sato, H.Watanabe, K.Shimizu, G.J.Hemink, and R.Shirota, “A novel side-wall transfer-transistor cell (SWATT cell) for multi-level NAND EEPROM’s,” in IEDM Tech. Dig., pp.275-278, Dec. 1995.
[10] S.Satoh, H.Hagiwara, T.Tanzawa, K.Takeuchi, and R.Shirota, "A Novel Isolation-Scaling Technology for NAND EEPROMs with the Minimized Program Disturbance," in IEDM Tech. Dig., pp. 291-294, Dec. 1997.
[11] A.Goda, W.Moriyama, H.Hazama, H.Iizuka, K.Shimizu, S.Aritome and R.Shirota, “A Novel Surface-Oxidized Barrier-SiN Cell Technology to improve Endurance and Read-Disturb Characteristics for Gigabit NAND Flash Memories.” In IEDM Tech. Dig., pp.771-774, Dec. 2000.
[12] F.Arai, S.Satoh, T.Yaegashi, E.Kamiya, Y.Matunaga, Y.Takeuchi, H.Kamata, A.Shimizu, N.Ohtani, N.Kai, S.Takahashi, W.Moriyama, K.Kugimiya, S.Miyazaki, T.Hirose, H.Meguro, K.Hatakeyama, K.Shimizu, R.Shiorta, “High Density(4.4F2) NAND Flash technology Using Super-Shallow Channel Profile(SSCP) engineering.” In IEDM tech. Dig., pp775-778, Dec. 2000. 
 
Ø      ISSCC
[13] Y.Itoh, M.Momodomi, R.Shirota, Y.Iwata, R.Nakayama, R.Kirisawa, T.Tanaka, K.Toita, S.Inoue, and F.Masuoka, “An Experimental 4Mb CMOS EEPROM with a NAND Structured Cell,” in ISSCC Dig. Tech. Papers, pp.134-135, Feb. 1989.
[14] K.Imamiya, Y.Sugiura, H.Nakamura, T.Himeno, K.Takeuchi, T.Ikehashi, K.Kanda, K.Hosono, R.Shirota, S.Aritome, K.Shimizu, K.Hatakeyama, and K.Sakui, “A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology,” in ISSCC Dig. Tech. Papers, pp.112-113, Feb. 1999.
 
Ø      VLSI technology
[16] R.Shirota, Y.Itoh, R.Nakayama, M.Momodomi, S.Inoue, R.Kirisawa, Y.Iwata, M.Chiba, and F.Masuoka, “A new NAND cell for ultra high density 5V only EEPROMs,” in Symp. VLSI Technology Dig. Tech. Papers, pp.33-34, June 1988.
[17] R.Kirisawa, S.Aritome, R.Nakayama, T.Endoh, R.Shirota, and F.Masuoka, "A NAND Structured Cell with a New Programming Technology for High Reliable 5 V-Only Flash EEPROM," in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1990.
[18] H.Watanabe, S.Aritome, G.J.Hemink, T.Maruyama, R.Shirota, “Sacling of tunnel oxide thickness for Flash EEPROMs Realizing Stress-Induced Leakage Current Reduction”, in Symp. VLSI Technology Dig. Tech. Papers, pp.47-45, June, 1994.
[19] H.G.Hemink, T.Tanaka, T.Endoh, S.Aritome, and R.Shirota, “Fast and accurate programming method for multilevel NAND flash EEPROM’s,” in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1995.
[20] S.Satoh, K.Shimizu, T.Tanaka, F.Arai, S.Aritome, and R.Shirota, “A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4Gbit NAND Flash memories,” in Symp. VLSI Technologies Dig. Tech. Papers, pp.108-109, June 1998.
[21] M.Ichige, Y.Takeuchi, K.Sugimae, A.Sato, M.Matsui, T.Kamigaki, H.Kutsukake, Y.Ishibashi, M.Saito, S.Mori, H.Meguro, S.Miyazaki, T.Miwa, S.Takahashi, T.Iguchi, N.Kawai, S.Tamon, N.Arai, H.Kamata, T.Minami, H.Iizuka, M.Higashitani, T.Pham, G.Hemink, M.Momodomi and R.Shirota, “A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs,” in Symp. VLSI technologies Dig. Tech. Papers, pp.89-90, June 2003.
 
Ø      VLSI Circuits
[22] T.Tanaka, M.Momodomi, Y.Iwata, Y.Tanaka, H.Oodaira, Y.Itoh, R.Shirota, K.Ohuchi, and F.Masuoka, “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.105-106, June 1990.
[23] T.Tanaka, Y.Tanaka, H.Nakamura, H.Oodaira, S.Aritome, R.Shirota, and F.Masuoka, “A Quick Intelligent Page-Programming Architecture 3V-Only NAND- EEPROMs,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.20-21, June 1992.
[24] T.Tanzawa, T.Tanaka, K.Takeuchi, R.Shirota, S.Aritome, H.Watanabe, G.Hemink, K.Shimizu, S.Sato, Y.Takeuchi, and K.Ohuchi, “A compact on-chip ECC for low cost Flash memories,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.59-60, June 1996.
 
Ø      Other Conferences
[25] M.Momodomi, Y.Iwata, T.Tanaka, Y.Ithoh, R.Shirota, F.Masuoka, “A high density NAND EEPROM with Block-page Programming for Micorcomputer Applications”, in IEEE CICC, pp.10.1.1-4, May, 1989.
 
[26] S.Aritome, R.Kirisawa, T.Endoh, N.Nakayama, R.Shirota, K.Sakui, K.Ohuchi, and F.Masuoka, “Extended Data Retention Characteristics after more than 104 Write and Erase Cycles in EEPROM’s,” in IEEE IRPS 1990, pp.259-264, 1990.
[27] S.Aritome, K.Hatakeyama, T.Endoh, T.Yamaguchi, S.Shuto, H.Iizuka, T.Maruyama, H.Watanabe, G.J.Hemink, T.Tanaka, M.Momodomi, K.Sakui, and R.Shirota, “A 1.13mm2 memory cell technology for reliable 3.3V 64M NAND EEPROMs,” in Extended Abstracts of SSDM, pp.446-448, Aug.1993.
[28] M.Momodomi, R.Shirota, K.Sakui, T.Endoh, and F.Masuoka, “Trend of NAND Flash memory and future development,” in International Workshop on Advanced LSI’s, pp.219-225, July 1995.
[29] K.Sakui, T.Tanaka, H.Nakamura, M.Momodomi, T.Endoh, R.Shirota, S.Watanabe, K.Ohuchi, and F.Masuoka, “A shielded bitline sensing technology for a high-density and low-voltage NAND EEPROM design,” in International Workshop on Advanced LSI’s, pp.226-232, July 1995.
[30] K.Sakui, Y.Itoh, R.Shirota, Y.Iwata, S.Aritome, T.Tanaka, K.Imamiya, J.Kishida, M.Momodomi, and J.Miyamoto, “Invited Paper: NAND Flash memory technology and future direction,” in IEEE 1997 NVSMW, pp.1-34, Feb. 1997.
[31] F.Arai, T.Maruyama and R.Shirota, “Extended Data Retention Process Tcdhnology for Highly Reliable Flash EEPROMs of 106 to 107 W/E Cycles”, in IEEE IRPS 1998, pp.378-382, April 1998.
[32] R.Shirota, “Invited paper: A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend.” in Non-Volatile Semiconductor Memory Workshop, pp.22-32, Feb.2000.
[33] R.Shirota, Test and repair of non-volatile commodity and embedded memories (NAND flash memory) “ in IEEE test Conference, pp.1221,Oct. 2002
[34] R.Shirota, “Invited paper:Future Trends in NAND-Type Flash Memory,” in Extended Abstracts of SSDM, pp.250-251, Aug.2004.
[35] R.Shirota, “Review of NAND Flash reliability,” in IEEE IRPS Tutorial notes, No.223, April 2005.
[36] R.Shirota, “NAND Flash Scaling and Technology Development” in Japan Semiconductor Technology Forum”, Jan. 2006.
[37] R.Shirota, “ Roadmap of the Flash Memory”, IEEE International Workshop on Digital Object Identifier in Memory Technology, Design, and Testing, MTDT, pp: xii – xii, Jun. 2006
[38] BREAKTHROUGH---Memory of the Future, The JAPAN, Journal, August, 2006
[39] R.Shirota, “Scaling trend of Flash memory for File storage”, in Memory, Tech, Design, Testing Workshop, pp.16, 2007.
[40] R.Shirota, “Review of recent development of high density Flash memory”, in New Non-Volatile Memory Workshop at ITRI, session B1, Nov. 2008.
[41] Hsin-Heng Wang, Chiu-Tsung Huang, Shin-Hsien Chen, Kuo, R, Sophia Liu, Ling-Kuey Yang, Houng-Chi Wei, Pittikoun, S., R.Shirota, Chin-chen Cho, ”A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory”, in VLSI-TSA International Symposium, pp.87 – 88, 2008.
[42] R.Shirota, “Review of Recent Flash Memory Development”, in Symposium on Nano Device Technology, Session 1.2, Apr. 2010.
[43] C.H.Liu, Y.M.Lin, R.Shirota, H.C.Wei, L.T.Kuo, C.Han.Liu, S.H.Chen, H.P.Wang, Y.Sakamoto, S.Pittikoun, “Self-Aligned Trench Isolation Recess Effect on Cell Performance and Reliability of 42nm NAND Flash Memory”, in VLSI-TSA, Session 3.1, Apr. 2010.
Publish Date Patent Title
2010/11/19
Ø      Registered US patent list
6, Non-volatile semiconductor memory device
US Pat. 5555204 - Filed Jun 28, 1994
18, Nonvolatile semiconductor memory device
US Pat. 6208560 - Filed Jun 22, 2000
23, MOS type semiconductor device
US Pat. 5172198 - Filed Jul 8, 1991
32, NAND type non-volatile semiconductor memory device
US Pat. 6859394 - Filed Mar 6, 2002
33, Method of making memory cell with shallow trench isolation
US Pat. 6274434 - Filed Nov 10, 1999
37, Semiconductor device and manufacturing method
US Pat. 6894341 - Filed Dec 23, 2002
40, Method of manufacturing NAND type EEPROM
US Pat. 5597748 - Filed May 23, 1994
42, Semiconductor device and method of fabricating the same
US Pat. 6680230 - Filed Jul 24, 2002
45, Semiconductor device and operation method thereof
US Pat. 6806525 - Filed Oct 24, 2002
47, Semiconductor device
US Pat. 6828627 - Filed Dec 23, 2003
49, Semiconductor device and method of manufacturing the same
US Pat. 6639296 - Filed Jun 15, 2001
51, Semiconductor integrated circuit device
US Pat. 7082055 - Filed Apr 19, 2005
52, Time limit function utilization apparatus
US Pat. 7208933 - Filed Jun 29, 2006
56, Time limit function utilization
US Pat. 7075284 - Filed Jul 3, 2003
59, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
US Pat. 11549770 - Filed Oct 16, 2006
61, Semiconductor memory device improved in data writing
US Pat. 7616491 - Filed Apr 23, 2007
62, METHOD OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE
US Pat. 11609614 - Filed Dec 12, 2006
66, Semiconductor memory device and electric device with the same
US Pat. 7151686 - Filed Sep 21, 2004
68, NONVOLATILE SEMICONDUCTOR MEMORY
US Pat. 11687758 - Filed Mar 19, 2007
70, Semiconductor Memory and Method of Manufacturing the Same
US Pat. 11858731 - Filed Sep 20, 2007

 
73, Fabrication method of a nonvolatile semiconductor memory
US Pat. 7141474 - Filed Dec 10, 2004
Country School Name Department Degree
Japan Nagoya University Physics Ph.D.
Japan Nagoya University Physics M.S.
Japan Nagoya University Physics B.S.