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Machine Learning Routes Chips

Post date:2016-04-08
ISPD design contest focused on FPGAs

4/8/2016 12:53 PM EDT 

SANTA ROSA, Calif.—The future of chip routing will be covered by the fastest machine learning methods—gone are auto-routing algorithms for billion transistors chips, according to the International Symposium of Physical Design 2016 (ISPD, 2016, April 3-6, Santa Rosa, Calif.) ISPD 2016 concluded its sessions with award ceremonies for best solution to its annual design contest and its best-paper awards, which featured machine learning of a power distribution network.

The ISPD 2016 contest was for the first time a routing problem for interconnecting a field-programmable gate array (FPGA). With Xilinx as the sponsor, the contest involved using a Xilinx 
XCVU095 FPGA, a part in the 20-nanometer Virtex UltraScale family (the XCVU095 has 67,200 configurable logic blocks (CLBs), 880 input/output (I/O) locations, 770 multiplier (DSP) locations, and 1730 block random access memory (BRAM) locations.

Best Paper Awar

This year's best paper award went to a doctoral candidate Wen-Hsiang Chang at National Chiao-Tung University. Chang won the best paper award with a little help from his friends (Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu and his advisor Mango C.-T. Chao from National Chiao-Tung University, Hsinchu, Taiwan, along with Cheng-Hong Tsai and Yen-Chih Chiu from Global Unichip Corporation, Hsinchu, Taiwan).

The paper, titled 
Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique was a breakthrough, according to the judges.

Continue reading on EE Times site.

Article originally posted on EE Times.

Last modification time:2016-05-17 PM 4:29

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