蘇朝琴
教授
姓名 蘇朝琴
電子郵件 ccsu@mail.nctu.edu.tw
聯絡電話 03-5712121 ext31310
研究專長 VLSI電路設計與測試、通信電路系統
0
教授簡介 類比積體電路導論(3),系統晶片設計聯合論文研討(5),混合信號積體電路測試,系統晶片設計聯合論文研討(5)
職稱 教授
年度 論文名稱
2014 Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, and Chen-Yi Lee, “A 48.6-to-105.2μW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications,” IEEE Journal of Solid-State Circuits. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 4, APRIL 2014

2013 Hung-kai Chen, Yingchieh Ho, and Chauchin Su, “Cumulative Differential Nonlinearity Testing of ADCs,” IEICE Trans. Fund. Electronics, Communications and Computer Sciences, vol.E-95A, no.10, pp. 1768-1775, Oct. 2012.
2013 Yingchieh Ho, Hung-kai Chen, Chiachi Chang and Chauchin Su, “Energy-effective Sub-threshold Interconnect Design Using High-Boosting Pre-drivers,” IEEE J. on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 307~313, June 2012.
2013 Yingchieh Ho, Yu-Sheng Yang, ChiaChi Chang, and Chauchin Su, “A Near-Threshold 480 MHz 78 μW All-Digital PLL with a Bootstrapped DCO,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 11, NOVEMBER 2013

2013  Tseng, Y. ;Ho, Y. ;  Kao, S. ;  Su, C. "A 0.09W Low Power Front-End Biopotential Amplifier for Biosignal Recording", Volume: PP  Page(s):Date of Publication :   21 Mar 2012
2012  Yingchieh Ho ;Chiachi Chang ;  Chauchin Su "Design of a Sub-threshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage Current Reduction Technique", Volume: 59, Page(s): 55 - 59 Date of Publication: Jan. 2012
2012 Ho, Yingchieh; Su, Chauchin "A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters", Volume: 47   Issue: 5   Pages: 1242-1251   DOI: 10.1109/JSSC.2012.2186722   Published: MAY 2012
2011 S.J. Jou C.C. Su, ``The Overview of Computer-Aided Design of Analog Circuits,"
Electronic Monthly, Feb. 1996, pp.67-76.
2011 C.C. Su, “The Overview of Analog Integrated Circuit Testing,” Electronic Monthly, Nov.
1996, pp.66-71.
2011 W. H. Hsieh, S. J. Jou and C. C. Su, “Parallel event-driven MOS timing simulator on
distributed memory multiprocessor,” IEE Proceedings Circuits, Devices and Systems,
Vol.143, No.4, August 1996, pp.207-212 (SCI)
2011 S. J. Jou, J. H. Pan, W. H. Hsieh, C. C. Su, “Current and power waveforms simulators for
CMOS circuits,” Journal of the Chinese Institute of Electrical Engineering, May 1997,
pp.141-148.
2011 S. J. Jou and I-Yao Chung, “Low-power self-timed circuit design technique,” Electronics
Letters,Vol.33 No.2, January 1997, pp.110-111. (SCI)
2011 S. J. Jou, C. Y. Chen, E. C. Yang and C. C. Su, “A pipelined Multiplier-Accumulator using
a high-speed, low power static and dynamic full adder design,” IEEE Journal of Solid-State
Circuits, Vol. 32, No. 1, January 1997,pp.114-118. (SCI)
2011 S. J. Jou, K. F. Liu and C. C. Su, "Circuits design optimization using symbolic approach,"
Journal of the Chinese Institute of Electrical Engineering, Feb. 1997, pp.51-60.
2011 S. J. Jou, M. F. Perng and C. C. Su, “Hierarchical techniques for symbolic analysis of
electrionic circuits,” IEE Proceedings Circuits, Devices and Systems, Vol. 144, No. 3, June
1997, pp.167-177. (SCI)
2011 C.C. Su, H.C. Lin, and S.J. Jou, “Design and Testing of a Mixed Signal Matched Filter for
IS-95 CDMA Code Acquisition,” Proc. National Science Council, ROC, Vol. 22, No. 1,
1998, pp.95-102.
2011 Y.J. Chang, C.L. Lee, J.E. Chen, and C.C. Su, "A Behavior Level Fault Model for the
Closed-loop Operational Amplifier," Journal of Information Science and Engineering. (EI)
2011 C.C. Su and S.J. Jou, "Decentralized BIST for 1149.1 and 1149.5 Based Interconnects,"
Journal of Electronic Testing - Theory and Applications, (JETTA), Vol. 15, No. 3, Dec.
1999, pp. 255-266. (SCI)
2011

J.W. Lin, C.L. Lee, C.C. Su, and J.E. Chen, "Fault Diagnosis for Linear Analog Circuits,"
Journal of Electronic Testing - Theory and Applications, (JETTA), Vol 17, 2001.
pp.483-491. (SCI)

2011 C.C. Su and W.L Tzeng, "Configuration Free SoC Interconnect BIST Methodology,"
Journal of Chinese Institute of Electrical Engineering. (EI)
2011 C.C. Su, Y.T. Chen, "Impulse Response Fault Model and Fault Extraction for Functional
Level Analog Circuit Diagnosis," Journal of Information Science and Engineering. (EI)
2011 C.C. Su and Y.T. Chen, "Intrinsic Response Extraction for the Analog Test Bus Parasitic
Effect Removal," IEEE Trans. On CAD, IEEE Trans. On Computer-Aided Design of
Integrated Circuits, Vol. 19, No. 4, April 2000, pp.437-445 (full paper). (SCI)
2011 C.C. Su, Y.T. Chen, and S.J. Jou, "Intrinsic Response for Analog Module Testing Using
Analog Testability Bus," ACM Transcations on Design Automation of Electronic Systems ,
Vol. 6, No.2, April 2001, pp.226-243 (full paper). (SCI)
2011 C.W. Lu, C.L. Lee, C.C. Su and J.E. Chen, “Analysis of Application of IDDQ Technique to
the Deep Submicron VLSI Testing,” Journal of Electronic Testing Technology and
Applications (JETTA), 18, pp.89-97, 2002. (SCI)
2011 W.C. Tsai, C.M. Huang, J.J. Wang, J.Y. Jou, and C.C. Su, “Design a Chip Within Half a
Day, iCEER 2005, 08-07, pp. 1-5.
2011 Wenliang Tseng, Chien-Nan Liu and Chauchin Su, “Passive Reduced-order Macromodeling
for Linear Time-delay Interconnect system,” IEICE Trans. On Electronics, vol. E89-C, no.11,
Nov.2006. (SCI)
2011 S.M. Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, and Jwu E Chen, “IEEE Standard
1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” IEEE Transaction
on CAD, Nov. 2006, pp.2513-2525. (SCI)
2011 K.S-M. Li, C.L. Lee, C.C. Su, J.E. Chen, “IEEE Standard 1500 Compatible Oscillation Ring
Test Methodology for Interconnect Delay and Crosstalk Detection,”, Journal of Electronic
Testing: Theory and Applications, August 2007, pp.341-355.
2011

S.M. Li, Y.W. Chang, C.L. Lee, C.C. Su, and J.E. Chen, “Multilevel Full-Chip Routing
With Testability and Yield Enhancement,” IEEE Trans. On Computer-Aided Design of
Integrated Circuits and Systems, Vol. 26, Issue. 9, Sept. 2007, pp. 1625-1636.

2011 Jen-Chien Hsu and Chauchin Su, “BIST for Measuring Clock Jitter of Charge-Pump
Phase-Locked Loops,” IEEE Transactions on Instrumentation and Measurement, Volume
57, Issue 2, pp. 276–285, 2008.
2011 Hungwen Lu, Chauchin Su, and Chien-Nan Jimmy Liu, “A Scalable Digitalized Buffer for
Gigabit I/O,” IEEE Transactions on CAS II, vol.55, issue.10, pp.1026-1030, October
2008.
2011 K.S-M. Li, C.L. Lee, C.C. Su, J.E. Chen, “A Unified Detection Scheme for Crosstalk
Effects in Interconnection Bus,” IEEE Trans. on Very Large Scale Integration Systems,
Vol.17, Iss.2, pp.306-311.
2011

Hungwen Lu, Chauchin Su, and Chien-Nan Jimmy Liu, “A Tree-Topology Multiplexer
for Multiphase Clocks System,” IEEE Transactions on CAS I, vol.56, issue.1, pp.124-131,
January 2009.

2011 Hungwen Lu, Hsinwen Wang, Chauchin Su, and Chien-Nan Jimmy Liu, “Design of an
All-Digital LVDS Driver,” IEEE Transactions on CAS I, vol.56, issue.8, pp.1635-1644,
August 2009.
2011 Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu, “Analysis and Design of Wide-Band
Digital Transmission in an Electrostatic-Coupling Intra- Body Communication System”
IEICE Trans. Comm, Vol. E92-B, No. 11,pp.3557-3563 Nov. 2009.
2011 Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu, “Measuring and Evaluating the
Bioelectrical Impedance of the Human Body Using Deconvolution of a Square
Waveform” IEICE Trans. Information and Systems, Vol.E93-D, No.6, pp.-, Jun. 2010.
2011 Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu, “Measuring the Transmission
Characteristic of the Human Body in an Electrostatic-Coupling Intra
Body Communication System using a Square Test Stimulus” IEICE Trans. Fundamentals
of Electronics, Communications and Computer Sciences, Vol. E93-A, No.3, pp.664-668,
Mar. 2010.
2011 Jenchien Hsu and Chauchin Su, “Timing Jitter and Modulation Profile Extraction for
Spread-Spectrum Clocks,” IEEE Transactions on Instrumentation and Measurement,
Volume 59, Issue 4, pp. 847-856, 2010.
2011 Ying-Chieh Ho, Ya-Ting Chen and Chauchin Su, ” A Power Efficient On-chip Bus
Design with Dynamic Voltage and Frequency Scaling Scheme,” International Journal of
Electrical Engineering, Vol. 17, No. 3, pp207-215, 2010.
年度 論文名稱
2013 Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Pei-Yu Hsu, Chien-Ying Yu, Yuhwai Tseng, Tze-Zheng Yang, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee,” A 48.6-to-105.2μW Machine-Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Monitoring,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2013' target='_blank'> Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Pei-Yu Hsu, Chien-Ying Yu, Yuhwai Tseng, Tze-Zheng Yang, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee,” A 48.6-to-105.2μW Machine-Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Monitoring,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2013
2013 Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Shiou-Ming Chuang, Tze-Zheng Yang, Chauchin Su, and Chen-Yi Lee,” A Sub-100uW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Application,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2012, pp. 156-157' target='_blank'>Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Shiou-Ming Chuang, Tze-Zheng Yang, Chauchin Su, and Chen-Yi Lee,” A Sub-100uW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Application,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2012, pp. 156-157
2013 Yingchieh Ho, Yu-Sheng Yang and Chauchin Su, “A 0.2-0.6 V Ring Oscillator Design Using Bootstrap Technique,” in IEEE Asian Solid-State Circuits Conference (ASSCC) Digest of Tech. Papers, Jeju, Nov. 14th-16th, 2011, pp. 333-336.

2013 Tsunhsin Wang, Yingchieh Ho, Yuhwai Tseng, and Chauchin Su, “A Hearing-Aid Front-End Circuit Based on Low Power And Low Area Mix Mode AGC” The 8th IASTED International Conference on Biomedical Engineering Biomed 2011, Feb.16-18, 2011, Innsbruck, Austria.

2011 Hung-Wen Lin, Ying-Chieh Ho, YingLin Fa, and ChauChin Su, "A 5Gb/s Pulse Signaling
Interface for Low Power On-Chip Data Communication," International Symposium on
Circuits and Systems, A1-L, pp. 201-204, 2010.
2011 Shuo-Ting Kao, Hung-Wen Lu, Chau-Chin Su, “A 1.5V 7.5uW Programmable Gain
Amplifier for Multiple Biomedical Signal Acquisition,” in Proceedings of IEEE
Biomedical Circuits and Systems Conference, November 2009.
2011 Wei-Chang Liu, Chih-Hsien Lin, Shyh-Jye Jou, Hung-Wen Lu, Chau-Chin Su, Kai-Wei
Hong, Kuo-Hsing Cheng, Shyue-Wen Yang, Ming-Hwa Sheu, “An illustration of
micro-network on chip with 10-Gb/s transmission links,” in Proceedings of Asia Solid
State Circuit Conference, November 2009.
2011 Hungwen Lu, Chauchin Su, and Chien-Nan Liu, ”A Scalable Digitalized Buffer for
Gigabit I/O,” in Proceedings of Custom Integrated Circuits Conference, pp.241-244,
September 2008.
2011 Jenchien Hsu; Maohsuan Chou; Chauchin Su, “Built-in jitter measurement methodology
for spread-spectrum clock generators,” in Proceedings IEEE International Symposium on
VLSI Design, Automation and Test, 2008, pp.67-72.
2011 H.K. Chen and Chauchin Su, “A test and diagnosis methodology for RF transceiver,” IEEE
2007 Asian Test Symposium, Oct. 2007.
2011 ChauChin Su, Po-Chen Lin, and HungWen Lu, “ An Inverter Based 2-MHz 42-uW delta
sigma ADC with 20-KHz Bandwidth and 66dB Dynamic Range,” Asia Solid State Circuit
Conference, Nov. 2006
2011 Maohsuan Chou, JenChien Hsu and Chauchin Su, “A Digital BIST Methodology for Spread
Spectrum Clock Generators” The Fifteenth Asian Test Symposium, Nov. 2006
2011 JenChien Hsu and Chauchin Su, “BIST for Jitter Measurement and Jitter Decomposition of
CDR,” IEEE International Mixed-Signals Testing Workshop, Jun. 2006.
2011 S.M. Li, Y.W. Chang, C.C. Su, C.L. Lee, J.E. Chen, “IEEE Std. 1500 Compatible
Interconnect Diagnosis for Delay and Crosstalk Faults,” Proc. 2005 ASPDAC, pp.366-371.
2011

Hsin Wen Wang, Hung Wen Lu, ChauChin Su, ”A Self-Calibrate All-Digital 3Gbps SATA
Driver Design” Proc. Asia Solid State Circuit Conference (ASSCC), Nov 2005, pp. 57-60.

2011 Hung Wen Lu, ChauChin Su, ” A 1.25 to 5Gbps LVDS Transmitter with a Novel
Multi-Phase Tree-Type Multiplexer” Proc. Asia Solid State Circuit Conference (ASSCC),
Nov 2005, pp. 389-392.
2011 Hung Wen Lu, Yin Tin Chang, ChauChin Su, "All digital 625Mbps & 2.5Gbps deskew
buffer design," Proc. VLSI Design, Automation and Test (VLSI-TSA-DAT), April 2005,
pp.263–266.
2011 Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su “A Spread Spectrum Clock
Generator for SATA-II,” Proc. International Symposium on Circuit and System
(ISCAS),May 2005
2011 JenChien Hsu and Chauchin Su, “BIST for Clock Jitter Measurement of Charge-Pump
Phase-Locked Loops,” Int’l Mixed Signal Test Workshop, 2005.
2011

K. S.M. Li, C.L. Lee, C.C. Su, J.E. Chen, “Oscillation Ring Based Interconnect Test Scheme
for SoC,” Proc. 2005 ASPDAC, pp. 184-187.

2011 S.M. Li, C.L. Lee, T.Q. Jiang, C.C. Su, J.E. Chen, “Finite State Machine Synthesis for
At-Speed Oscillation Testability,” Proc. 2005 Asian Test Symposium, pp. 360-365.
2011 S.M.Li, C.L. Lee, Y.W. Chang, C.C. Su, J.E. Chen, “Multi-Level Routing With Testability
and Yield Enhancement,” Proc. 2005 Int’l Workshop on System Level Design.
2011

H.W. Lu and C.C. Su, “A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type
Multiplexer,”Proc. 2004 IEEE Asia-Pacific Conference on Advanced System Integrated
Circuits (AP-ASIC), pp. 228-231.

2011 H.W. Wang, H.W. Lu, and C.C. Su, “A Digitized LVDS Driver with Simultaneous
Switching Noise Rejection,” Proc. 2004 IEEE Asia-Pacific Conference on Advanced System
Integrated Circuits (AP-ASIC), pp. 240-243.
2011 C.C. Su, C.S. Chang, H.W. Huang, D.S. Tu, C.L. Lee, and J. CH. Lin,“Dynamic Analog
Testing via ATE Digital test Channels, ” Proc. 2004 IEEE Asian Test Symposium, pp.
308-312.
2011 K. SM. Li, C.L. Lee, C.C. Su, and J.E. Chen, “A Unified Approach to Detecting Crosstalk
Faults of Interconnected in Deep Submicron VLSI,”Proc. 2004 IEEE Asian Test Symposium,
pp. 145-150.
2011 H.K. Chen and C.C. Su,“A Deconvolution Based RF Test Methodology,”2004 IEEE
International Mixed Signal Test Workshop.
2011 Chauchin Su; Chih-Hu Wang; Wei-Juo Wang; Tseng, I.S.; "1149.4 based on-line quiescent
state monitoring technique," Proc. IEEE 2003 VLSI Test Symposium (VTS 2003). May
2003, pp. 197 -202.
2011 Shi-Dai Mai; Lune, H.; Ren-Chien Hsu; Chauchin Su; "An autonomous multiple module
clock synchronization methodology for SoC," Proc. IEEE 2003 International System on
Chip Conference (SoC 2003), Sept. 2003, pp. 39 -42.
2011 Chauchin Su; Wei-Juo Wang; Chih-Hu Wang; Tseng Is; "A novel LCD driver testing
technique using logic test channels," Proc. 2003 Asia and South Pacific (ASP-DAC 2003),
Jan. 2003, pp. 657 -662. (Invited)
2011 Wenliang Tseng; Sonfu Yeh; Pojen Huang; Chauchin Su; "Qualitative analysis of coupled
transmission lines," Proc. 2003 Electronic Components and Technology Conference (ECTC
2003), May 2003, pp. 1656 -1663.
2011 Wenliang Tseng; Pojen Huang; Sonfu Yeh; Chauchin Su; "Equivalent circuits for the
qualitative analysis of the transmission line reflection effects," Proc. 2002 Electrical
Performance of Electronic Packaging Conference (EPEP 2002), Oct. 2002, pp. 145 -148.
2011 C.C. Su and W.L Tzeng, "Configuration Free SoC Interconnect BIST Methodology," Proc.
2001 Int'l Test Conference (ITC 2001), Baltimore, Maryland, Oct. 2001 (to appear).
2011 Y.T. Chen and C.C. Su, "Test Waveform Shaping in Mixed Signal Test Bus by
Pre-Equalization," Proc. 2001 VLSI Test Symposium (VTS 2001), Marina Beach, Los
Angles, U.S.A. pp.260-265.
2011 C.C. Su, et. al., "A Computer Aided Engineering System for Memory BIST," Proc. 2001
Asia and South Pacific Design Automation Conference, 2001.
2011 C.C. Su, et. al., "A Computer Aided Engineering System for Memory BIST," Proc. 2001
Asia and South Pacific Design Automation Conference, 2001.
2011 J.W. Lin, C.L. Lee, C.C. Su, and J.E. Chen, "Fault Diagnosis for Linear Analog Circuits,"
Proc. 9th Asian Test Symposium, 2000, pp. 25-30.
2011 Y.C. Huang, C.L. Lee, J.W. Lin, J.E. Chen and C.C. Su, "A Methodology for Fault Model
Development for Hierarchical Linear Systems," Proc. 9th Asian Test Symposium, 2000, pp.
90-95.
2011 C.W. Lu, C.L. Lee, C.C. Su, and J.E. Chen, "Is IDDQ Testing Not Applicable for Deep
Submicron VLSI in Year 2011?" Proc. 9th Asian Test Symposium, 2000, pp. 338-343.
2011 C.W. Lu, C.L. Lee, C.C. Su, and J.E. Chen, "Is IDDQ Testing Not Applicable for Deep
Submicron VLSI in Year 2011?" Proc. 9th Asian Test Symposium, 2000, pp. 338-343.
2011 C.C. Su, et. al., "A Distributed At-Speed TDBI Memory Test System", Proc. 2000 Test
Resource Partitioning Workshop, Oct. 2000.
2011 C.C. Su, Y.T. Chen, M.J. Huang, G.N. Chen, and C.L. Lee, “All Digital Built-in Delay and
Crosstalk Measurement for On-Chip Buses,” Proc. 2000 IEEE Design, Automation and Test
in Europe (DATE 2000), Paris, France, March 2000.
2011 Y.T. Chen and C.C. Su, “Crosstalk Effect Removal for Analog Measurement in Analog Test
Bus”, Proc. 2000 IEEE VLSI Test Symposium (VTS 2000), Montreal, Canada, May 2000.
2011 C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
Environment,” 1999 Asian Test Symposium, Nov. 1999, pp. 233-239.
2011 C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
Environment,” 1999 Asian Test Symposium, Nov. 1999, pp. 233-239.
2011 C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
Environment,” 1999 Asian Test Symposium, Nov. 1999, pp. 233-239.
2011 C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
Environment,” 1999 Asian Test Symposium, Nov. 1999, pp. 233-239.
2011

C.C. Su, L.Y. Huang, J.J. Lee, and C.K. Wang, “A Frame-Based Symbol Timing Recovery
for Large Pull-in Rang and Small Steady Sate Variation,” Proc. 1999 Asia Pacific
Conference on ASICs, 1999, pp. 75-78.

2011 C.C. Su, “A Linear Optimal Test Generation Algorithm for Interconnect Testing,” Proc.
1998 IEEE Int’l Conference on Computer Aided Design, 1998, pp. 290-295
2011 C.C. Su, S.J. Jeng, and Y.T. Chen, “Boundary Scan BIST Methodology for Reconfigurable
Systems,” Proc. 1998 IEEE Int’l Test Conference, 1998 774-783.
2011 Y.T. Chen and C.C. Su, “Analog Module Metrology Using MNABST-1 P1149.4 Test
Chip,” Proc. IEEE Asian Test Symposium, 1998 378-382.
2011 C.C. Su, “Comprehensive Interconnect BIST Methodology for Virtual Socket Interface,”
Proc. IEEE Asian Test Symposium, 1998, pp.259-263.
2011

Chih-Wen Lu; Chung Len Lee; Chen, J.E.; Chauchin Su; "A new IDDQ testing scheme
employing charge storage BICS circuit for deep submicron CMOS ULSI," Proc. 1998
International Workshop on IDDQ Testing, November 1998, pp. 54 -58.

2011 C.C. Su, Y.T. Chen, and S.J. Jou, ``Parasitic Effect Removal for Analog Measurement in
P1149.4 Environment," Proc. 1997 IEEE Int'l Test Conference, 1997.
2011 C.C. Su, Y.R. Cheng, Y.T. Chen, and S. T, ``Analog Signal Metrology for Mixed Signal
ICs," Proc. 1997 IEEE Asia Test Symposium, 1997.
2011 C.C. Su, Hung-Chi Lin, and Shye-Jye Jou, ``Mixed Signal Design of Cascadable Matched
Filters," Proc. 1997 IEEE Int'l Symp. on Circuits and Systems, 1997.
2011 C.C. Su, Chenq-Fan Yen, and Jang-Chuang Yo, ``Hardware Efficient Updating Technique
for LZW CODEC Design," Proc. 1997 IEEE Int'l Symp. on Circuits and Systems, 1997.
2011 C.C. Su, K.Y. Chen, and S.J. Jou, ``Structural Approach for Performance Driven ECC
Circuit Synthesis," Proc. 1997 Asian and South Pacific Design Automation Conference,
1997.
2011 Design, 1996.' target='_blank'>C.C. Su, Yue-Tsang Chen, Shyh-Jye Jou, and Yuan-Tzu Ting, ``Metrology for Analog
Module Testing Using Analog Testability Bus," Proc. 1996 Int'l Conf. on Computer Aided
Design, 1996.
2011 C.C. Su, Shyh-Shen Hwang, Shyh-Jye Jou, and Yuan-Tzu Ting, ``Syndrome Simulation and
Syndrome Test for Unscanned Interconnects," Proc. 1996 Asian Test Symposium, 1996.
2011 C.C. Su, S.J. Jou, and Y.T. Ting, ``Decentralized BIST for 1149.1 and 1149.5 Based
Interconnects," Proc. 1996 European Design and Test Conference, pp. 120-125 1996.
2011 S.C. Yin, C.C. Su, et.al., ``A New VSB Modulation Technique and Shaping Filter Design,"
Proc. 1996 Int'l Symp. on Circuits and Systems, 1996.
2011 Design, San Jose CA USA, pp.631-636. 1995.' target='_blank'>C.C. Su, S.S. Chiang, S.J. Jou, ``Impulse Response Fault Model and Fault Extraction for
Functional Level Analog Circuit Diagnosis," Proc. Int'l Conference on Computer Aided
Design, San Jose CA USA, pp.631-636. 1995.
2011 Design, San Jose CA USA, pp.631-636. 1995.' target='_blank'>C.C. Su, S.S. Chiang, S.J. Jou, ``Impulse Response Fault Model and Fault Extraction for
Functional Level Analog Circuit Diagnosis," Proc. Int'l Conference on Computer Aided
Design, San Jose CA USA, pp.631-636. 1995.
2011 Shyh-Jye Jou; Kou-Fong Liu; Chauchin Su; "Circuits design optimization using symbolic
approach," Proc. IEEE 1995 International Symposium on Circuits and Systems, April 1995,
pp. 1396 -1399 vol.2.
2011 Washington DC USA, Oct. 1994, pp.670-676.' target='_blank'>C.C. Su, K.C. Hwang, and S.J. Jou, ``An IDDQ Based Built-in Concurrent Test Technique
for Interconnects in a Boundary Scan Environment," Proc. IEEE Int'l Test Conference,
Washington DC USA, Oct. 1994, pp.670-676.
2011 C.C. Su, ``Random Testing Methodologyof Interconnects in a Boundary Scan Environment,"
Proc. 1994 European Design and Test Conference, Paris France, Feb. 1994, pp. 226-231.
2011 C.C. Su, and K.C. Hwang, ``A Serial Scan Test Vector Compression Mthodology," Proc.
IEEE Int'l Test Conference, Baltimore MD USA, Oct. 1993, pp.981-988.
2011 C.Y. Chang and C.C. Su, ``An Universal BIST Methodology for Interconnects," Proc. IEEE
Int'l Symp. on Circuits and Systems, Chicago IL USA, May 1993, pp.1615-1618.
2011 Circuits and Systems, Chicago IL USA, May 1993, pp.1706-1709.' target='_blank'>
60. C.C. Su and J.H. Wang, ``A Synthesis Tool for ECC Circuits," Proc. IEEE Int'l Symp. on
Circuits and Systems, Chicago IL USA, May 1993, pp.1706-1709.
2011 on Circuits and Systems, San Diego, CA USA, May 1992, pp.411-414.' target='_blank'>C.C. Su}, et. al., ``A BIST Methodology for Iterative Logic Arrays," Proc. IEEE Int'l Symp.
on Circuits and Systems, San Diego, CA USA, May 1992, pp.411-414.
2011 S.J. Jou, C.Y. Chen, E.C. Yang, and C.C. Su, ``A Pipelining Multiplier Accumulator Using
a High Speed Low Power Static and Dynamic Full Adder Design," IEEE Custom Integrated
Circuits Conference, May 1995, pp. 27.6.1-27.6.4.
2011 USA, May, 1995, pp. 139-1399.' target='_blank'>W.H. Shieh, S.J. Jou, and C.C. Su, ``A Parallel Even-Driven MOS Timing Simulator for
Distributed Memory Multiprocessor," Proc. Int'l Symp. on Circuits and Systems, Seatle
USA, May, 1995, pp. 139-1399.
2011 S.J. Jou, K.F. Liu, and C.C. Su, ``Circuit Design Optimization Using Symbolic Approach,"
IEEE Int'l Symp. Circuits and Systems, Seatle USA, May 1996, pp. 574-577.
2011 U.K., May, 1994.' target='_blank'>S.J. Jou, M.F. Perng, C.C. Su, and C.K. Wang, ``Hierarchical Techniques for Symbolic
Analysis of Large Electronic Circuits," Proc. Int'l Symp. on Circuits and Systems, Landon,
U.K., May, 1994.
2011 Chou-Ming Kuo, Ying-Chieh Ho and Chauchin Su, ” A 4-bit 5-GSample/s Low-Power
Digitalized A/D Converter for Pulse Amplitude Modulation System,” 21th VLSI Design and
CAD Symposium, Aug. 2010.
2011 Ya-Ting Chen, Ying-Chieh Ho and Chauchin Su, ” A Power Efficient On-chip Bus Design
with Dynamic Voltage and Frequency Scaling Scheme,” 20th VLSI Design and CAD
Symposium, Aug. 2009.
2011 H.W. Lu, C.C. Yang, J.M. Shih and C.C. Su, " A 10Gb/s/pin Transceiver for On-Chip Bus
with All-Digital SerDes Scheme," 20th VLSI Design and CAD Symposium, Aug. 2009.
2011 H.W. Lu, J.M. Shih and C.C. Su, " All-Digital Resonant DCO with Inverter-based Tunable
Active Inductor," 20th VLSI Design and CAD Symposium, Aug. 2009.
2011 S.-T. Kao, H.W. Lu, S.M. Chuang and C.C. Su, " A Low Power Analog Front-End for
Biomedical Signal Recording," 20th VLSI Design and CAD Symposium, Aug. 2009.
2011 S.-T. Kao, H.W. Lu, S.M. Chuang and C.C. Su, " A 1.5-V Programmable Front-End
Bio-Potential Signal Acquisition IC," 20th VLSI Design and CAD Symposium, Aug. 2009.
2011

JenChien Hsu and Chauchin Su,“BIST for Measuring Signal Eye Opening in High Speed
I/O”, 19th VLSI Design and CAD Symposium, Aug. 2008.

2011 H.W. Lu and C.C. Su, "A Scalable Digitalized Buffer for Gigabit I/O," 19th VLSI Design
and CAD Symposium, Aug. 2008.
2011 H.W. Lu, KuanYu Chen, Chau-Chin Su, “A Low Power Tree-Type Multiplexer with
embedded timing skew switch, ” 18th VLSI Design and CAD Symposium, Aug. 2007.
2011 H.W. Lu, KuanYu Chen, Chau-Chin Su, “A Digitalize LVDS Driver with Output Level
Self-Calibrate and Pre-Emphasis,” 17th VLSI Design and CAD Symposium, Aug. 2006.
2011 H.W. Lu and C.C. Su, “A 2.5Gbps Digitalize LVDS Transceiver design,” 15th VLSI Design
and CAD Symposium, Aug. 2004.
2011

H.W. Wang, H.W. Lu and C.C. Su, “A Digitized LVDS Driver with Simultaneous
Switching Noise Rejection, ” 15th VLSI Design and CAD Symposium, Aug. 2004.

2011 H.W. Lune and C.C. Su, "A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type
Multiplexer," Proc. 14th VLSI Design and CAD Symposium, Aug. 2003, pp. 62-65.
2011 W.L Tseng, S.F, Yeh, P. H. Huang, and C. C. Su, "Qualitative Analysis of N-Coupled
Transmission Lines," Proc. 14th VLSI Design and CAD Symposium, Aug. 2003, pp.
289-292.
2011 W.L Tseng, S.F. Yeh, P.J, Huang, and C.C. Su, "Literal Reflection Effect Equivalent
Circuits of Transmission Line Analysis," Proc. 13th VLSI Design and CAD Symposium,
Aug. 2002, pp. 293-296.
2011 C.C. Su, C.H. Lin, and C.L. Hu, "A Sigma-Delta Modulation Based Carrier Recovery
Architecture for the ATSC HDTV," Proc. 11th VLSI Design/CAD Symposium, Aug. 2000,
pp.293-296.
2011 C.C. Su, G.N Chen, and Y.T. Chen, "A Design for Diagnosis Technique for the Delay and
Crosstalk Measurement of On-Chip Bus Wires," Proc. 11th VLSI Design/CAD Symposium,
Aug. 2000, pp.293-296.
2011 Y.C. Huang, C.L, Lee, J.E. Chen, and C.C. Su, “Hierarchical Fault Model,” Proc. 10th VLSI
Design/CAD Symposium, Aug. 1999, pp. 199-202
2011 Y.T. Chen and C.C. Su, “Parasitic Effect Removal for Analog Measurement in MNABST-1
P1149.4 Test Chip Environment,” Proc. 9th VLSI Design/CAD Symposium, Aug. 1998,
pp.181-184.
2011 J.S. Liu, Y.H. Jaeng, and C.C. Su, “Code Tracking Loop for the Synchronization of IS-95
CDMA,” Proc. 9th VLSI Design/CAD Symposium, Aug. 1998, pp.219-222.
2011 S.J. Kuo, C.L. Lee, J.E. Chen, and C.C. Su, “A Fault Diagnosis Technique for Delta-Sigma
Analog to Digital Converters,” Proc. 9th VLSI Design/CAD Symposium, Aug. 1998,
pp.133-136.
2011 C.C. Su and Y.T. Chen ``BIST Methodology for Comprehensive Interconnect Testing,”
Proc. 8th VLSI Design/CAD Symposium, Aug. 1997, pp.73-76.
2011 C.C. Su, Y.R. Cheng, Y.T. Chen, and S. Tenchen, ``Analog Signal Metrology by on-chip
ADCs of Mixed Signal ICs,” Proc. 8th VLSI Design/CAD Symposium Aug. 1997,
pp.185-188.
2011 S.T. Yin, C.C. Su, M.T. Shieu, C.K. Wang, and W.I. Way, ``A New VSB Modulation
Techniques and Shaping Filter Design," Proc. 6th VLSI Design /CAD Symposium, Chia-Yi
Taiwan ROC, Aug. 1995, pp.120-123.
2011 Shieh, S.J. Jou, and C.C. Su, ``Network Hopping Technique for Simulation Tools," Proc.
6th VLSI Design /CAD Symposium, Chia-Yi Taiwan ROC, Aug. 1995, pp.302-305.
2011 Jou, C.Y. Chen, and C.C. Su, ``Implementation of High Performance
Multiplier/Accumulator," Proc. 6th VLSI Design /CAD Symposium, Chia-Yi Taiwan ROC,
Aug. 1995, pp.155-160.
2011 Lin, C.C. Su, C.K. Wang, and S.J. Jou, ``MixCAD - A Behavioral Level Mixed Mode
System Simulator," Proc. 5th VLSI Design /CAD Symposium, Tainan Taiwan ROC, Aug.
1994, pp.269-274.
2011 Jou, C.Y. Chen, C.C. Su, and C.K. Wang, ``Implementation of High Performance
Multiplier/Accumulator," Proc. 5th VLSI Design /CAD Symposium, Tainan Taiwan ROC,
Aug. 1994, pp.155-160.
2011 Hsieh, S.J. Jou, and C.C. Su, ``PMOTA - A Parallel Event-Driven MOS Timing Simulator
for Distributed Memory Multiprocessors," Proc. 5th VLSI Design /CAD Symposium, Tainan
Taiwan ROC, Aug. 1994, pp.299-303.
2011 Jou, H.F. Liu, and C.C. Su, ``Integrated Circuits Design Optimization Using Symoblic
Approach," Proc. 5th VLSI Design/CAD Symposium, Tainan Taiwan ROC, Aug. 1994,
pp.310-314.
計畫類別 年度 計畫名稱 參與人 職稱/擔任之工作 計畫期間 補助/委託或合作機構
研究計畫 2013 多重生醫訊號檢測模組與封裝之基礎技術研發 蘇朝琴 共同主持人 2013.11 ~ 2014.10 行政院國家科學委員會
研究計畫 2013 具通訊與容錯功能之智慧車用電池模組管理系統-總計畫暨子計畫一 蘇朝琴 主持人 2013.08 ~ 2014.07 行政院國科會
研究計畫 2012 具通訊與容錯功能之智慧車用電池模組管理系統-總計畫暨子計畫一 蘇朝琴 主持人 2012.08 ~ 2013.07 行政院國科會
研究計畫 2012 智慧電子國家型科技計畫研究發展及推動規劃(2/2) 蘇朝琴 主持人 2012.01 ~ 2013.02 行政院國家科學委員會
研究計畫 2011 智慧電子國家型科技計畫研究發展及推動規劃(1/2) 蘇朝琴 主持人 2011.08 ~ 2011.12 行政院國家科學委員會
研究計畫 2011 具通訊與容錯功能之智慧車用電池模組管理系統-子計畫一:車用電池陣列之電源管理與容錯設計(I) 蘇朝琴 主持人 2011.08 ~ 2012.07 行政院國家科學委員會
研究計畫 2011 具通訊與容錯功能之智慧車用電池模組管理系統-總計畫(I) 蘇朝琴 主持人 2011.08 ~ 2012.08 行政院國家科學委員會
研究計畫 2011 未來世代內嵌式SRAM設計技術3年計畫 蘇朝琴、黃威、莊景德、周世傑、蘇彬、趙家佐、張錫嘉、鄭國興 總主持人 2011.05 ~ 2012.07 財團法人資訊工業策進會
研究計畫 2010 具通信功能之車用功率系統晶片-子計畫四:多功能車用功率積體電路(3/3) 蘇朝琴 主持人 2010.08 ~ 2011.07 行政院國家科學委員會
研究計畫 2010 具通信功能之車用功率系統晶片-總計畫(3/3) 蘇朝琴 主持人 2010.08 ~ 2011.07 行政院國家科學委員會
研究計畫 2010 微瓦級動態電壓與頻率調整之晶片匯流排設計(2/2) 蘇朝琴 主持人 2010.08 ~ 2011.07 行政院國家科學委員會
研究計畫 2010 未來世代內嵌式SRAM設計技術3年計畫 蘇朝琴、黃威、莊景德、周世傑、蘇彬、趙家佐、張錫嘉、鄭國興 總主持人 2010.05 ~ 2011.04 財團法人資訊工業策進會
研究計畫 2009 具通信功能之車用功率系統晶片-子計畫四:多功能車用功率積體電路(2/3) 蘇朝琴 主持人 2009.08 ~ 2010.07 行政院國家科學委員會
研究計畫 2009 具通信功能之車用功率系統晶片-總計畫(2/3) 蘇朝琴 主持人 2009.08 ~ 2010.07 行政院國家科學委員會
研究計畫 2009 微瓦級動態電壓與頻率調整之晶片匯流排設計(1/2) 蘇朝琴 主持人 2009.08 ~ 2011.07 行政院國家科學委員會
研究計畫 2009 未來世代內嵌式SRAM與STT-MRAM設計技術三年計畫 蘇朝琴、黃威、莊景德、周世傑、蘇彬、趙家佐、張錫嘉、鄭國興 總主持人 2009.05 ~ 2010.04 財團法人資訊工業策進會
研究計畫 2008 具通信功能之車用功率系統晶片-子計畫四:多功能車用功率積體電路(1/3) 蘇朝琴 主持人 2008.08 ~ 2009.07 國科會
研究計畫 2008 具通信功能之車用功率系統晶片-總計畫(1/3) 蘇朝琴 主持人 2008.08 ~ 2009.07 國科會
研究計畫 2008 高速序列傳輸電路之自我測試設計、實作、與分析(3/3) 蘇朝琴 主持人 2008.08 ~ 2009.07 國科會
發表日期 專利名稱
2014/06/11

張家齊、何盈杰、蘇朝琴低功率靴帶式反相器電路 中華民國發明專利,發明第I 401885號,2013.07.11~2030.11.23

2014/06/11  蘇朝琴、何盈杰、黃博祥使用共用傳導層傳送晶片間多重信號之系統中華民國發明專利,發明第I 430426號,2014.03.11~2030.10.18
2014/06/11  何盈杰、蘇朝琴數位式全差動放大器電路 中華民國發明專利,申請號:099140593,申請日:99.11.24,已核淮待領證。

2014/06/11  “RING OSCILLATOR” Yingchieh Ho、楊于昇、Chauchin Su, US Patent, 已核淮待領證。

2013/11/20 Chauchin SuYingchieh Ho、黃博祥“Chip-to-chip Multi-signaling Communication System with Common Conduction Layer”, US Patent, US 8,426,980 B22013.04.23~2031.08.16.' target='_blank'>Chauchin SuYingchieh Ho、黃博祥“Chip-to-chip Multi-signaling Communication System with Common Conduction Layer”, US Patent, US 8,426,980 B22013.04.23~2031.08.16.
2013/11/20 I3589022012/02~2027/12' target='_blank'> 呂鴻文、蘇朝琴,『信號延遲電路』,中華民國發明專利,發明第 I3589022012/02~2027/12
2011/07/20 Chauchin Su, Lee-Yuang Huang, Jin-Jyh Lee, Chorng-Kuang Wang, "Method and Circuit
for Sampling Timing Recovery," US Patent 6,366,628,2002.4.2.
2011/07/20 Chauchin Su, Ming-Hwa Hue, and Chorng-Kuang Wang, "Architecture of
Non-Synchronous Open Loop Demodulation Circuit in Pulse Position Modulation," US
Patent, 6,292,051, 2001,9.18.
2011/07/20 Chauchin Su, H.M. Tseng, IS, Tseng, C.H. Lin, C.M. Yang, "Timing Generation Aparatus
with Calibration Capability," US Patent, 6,304,119, 2001.10.16.
2011/07/20 I.S. Tsent, T.Y. Hsien, Chauchin Su, W.J. Wang, “Method and System for Measuring
Characteristics of Liquid Crystal Display Driver Chip,” US Patent, 6,925,415, 2005.8.2.
2011/07/20 Chauchin Su, S.H. Lin, L.T. Wang, “IEEE Std. 1149.4 Compatible Analog BIST
Methodology,” US Patent, 7,228,479, 2007. 6. 5.
2011/07/20 Jenchien Hsu, Hungwen Lu, Chauchin Su, YeongJar Chang, " Sample and hold circuit and
related data signal detecting method utilizing sample and hold circuit, " US Patent,
11/854,560, 2007.8.13.
2011/07/20 Jenchien Hsu, Hungwen Lu, Chauchin Su, YeongJar Chang , " Built-in jitter measurement
circuit," US Patent, 11/870,113, 2007.10.25
2011/07/20 Hungwen Lu and Chauchin Su , "Buffer circuit, " US Patent, 20080150583, 2008.6.26.
2011/07/20 Hungwen Lu and Chauchin Su, "Signal delay circuit," US Patent, 12/193,286, 2008.8.18.
2011/07/20 Chauchin Su, Cheinhsi Lee, Hungwen Lu, Hsuehchin Lin, Yenpin Tseng, Chianan Wang,
Uanjiun Liu, "High-speed serial link clock and data recovery," US Patent, 7,415,089,
2008.8.19.
2011/07/20 Hungwen Lu and Chauchin Su, "Oscillator circuit ," US Patent, 20080315966, 2008.12.25.
2011/07/20 Chauchin Su, Hungwen Lu, Shunmin Chi, " Self-Calibrating High-Speed Analog-to-Digital
Converter, " US Patent, 7,474,239, 2009.1.6.
2011/07/20 汪重光、薛木添、黃光虎、蘇朝琴,『用於一時序回復系統和自動增益控制系統之數
位 / 類比式頻關調整器』,中華民國專利,台專﹝五﹞04033 字第847367 號。
2011/07/20 蘇朝琴、黃李源、李錦智、汪重光,『取樣時序恢復電路』,中華民國專利 發明第
106364 號,1999.8.11~2008.6.2。
2011/07/20 蘇朝琴、胡明華、汪重光,『脈衝位置調變之非同步開迴路解調電路架構』,中華民
國發明專利,126190,2001.1.21~2008.10.18。
2011/07/20

蘇朝琴、楊駿民、曾一士、張莒林,『時序延遲產生電路及裝置』,中華民國發明專
利,公告 編號 447190,2001.7.21。

2011/07/20 蘇朝琴、鄭丁元,『資料區框時序回覆電路之即刻頻率及相位補償技術』,中華民國
發明專利,公告 編號 437220,2001.5.28。
2011/07/20 蘇朝琴、陳雨蒼、黃慕真、陳耿男,『匯流排時間延遲與交談失真之可偵錯設計技術』,
中華民國專利,公告編號 460780,2001.10.21。
2011/07/20 蘇朝琴,『單晶片測試機積體電路』,中華民國發明專利,公告編號 449849,2001.8.11。
2011/07/20 蘇朝琴、張家祥,『多重模組相位同步系統架構』,中華民國發明專利申請中,2001.
7. 28。
2011/07/20

蘇朝琴、陳雨蒼、曾一士,『改良量測設備測量方法』,中華民國發明專利,公告編
號 472150,2002.1.11。

2011/07/20 曾一士、蘇朝琴、王偉洲,『液晶顯示器驅動晶片量測裝置及其量測方法』,中華民
國發明專利,公告編號:581873,2002.3.5。
2011/07/20 蘇朝琴、胡嘉琳,『全數位延遲線迴路系統架構』,中華民國發明專利,483257,
2002.4.11~2021.7.31。
2011/07/20 蘇朝琴、林志鴻、胡嘉琳,『載波回覆電路』,中華民國發明專利,發明第476225,
2002.2.11~2020. 6.27。
2011/07/20

蘇朝琴、陳雨蒼、曾一士,『測試設備改良信號傳輸通道的方法』,中華民國發明專
利,公告編號:523591,2003.3.1。

2011/07/20 蘇朝琴、張家祥,『多重模組相位同步系統架構』,中華民國專利 I233725,2005. 6. 1.
2011/07/20

蘇朝琴、王信文、呂鴻文,『可抑制同步切換雜訊電路』,中華民國發明專利,專利證
書號:I241766,公告日期:2005.10.11。

2011/07/20 蘇朝琴、莊英廷、呂鴻文,"通訊傳輸機之數位相位校正緩衝器與其操作方法",中華民國
發明專利,專利證書號:I239144,公告日期:2005.9.01。
2011/07/20 蘇朝琴、李建錫、呂鴻文、林學錦、曾硯彬、王家男、劉萬鈞,"高速串列鏈結時脈及
資料回復系統及方法",中華民國專利 I268055,2006.12.01。
2011/07/20

蘇朝琴、呂鴻文、陳俊銘,"多相位數位控制震盪器架構",中華民國專利 I272770,
2007.2.1.

2011/07/20 蘇朝琴、李建錫、呂鴻文,"傳輸機之時脈與資料回復裝置與其操作方法",中華民國
專利 I286016, 2007.8.21.
2011/07/20 陳冠宇、呂鴻文、蘇朝琴,"低功率低面積之樹狀多工器架構",中華明國專利申請中,
公告編號: 0951261150,公告日期:95.7.18
年度 實驗室名稱 位置
混合信號電路實驗室 工五館 918室
國家 學校名稱 系所 學位 期間
美國 威斯康辛大學 電機電腦工程 博士 1983.08 ~ 1989.12
服務機關名稱 單位 職務 期間
元智大學 電機系諮議委員會 諮議委員 2012.01 ~ 2014.12
經濟部 技術審查委員會 主審委員 2012.01 ~ 2014.12
思源科技教育基金會 董事長 2011.01 ~ 2013.12
交通大學 電機系 教授兼系主任 2009.08 ~ 2011.07
教育部 顧問室 顧問 2008.08 ~ 2012.07
晶片系統國家型科技計畫 計畫辦公室 執行長 2004.01 ~ 2007.05
交通大學 電控系 教授教授且兼任交通大學電子資訊中心副主任 2002.08 ~ 2008.07
中央大學 電機系 教授 2000.08 ~ 2002.07
類別 年度 獎項名稱 頒獎單位
校外榮譽事項 2013 旺宏金矽獎,銀賞”用於可攜式行動照護的微瓦級多功能心臟訊號感測處理單晶片”. 旺宏教育基金會
校外榮譽事項 2012 旺宏金矽獎,銀賞”臨界電壓晶片資料傳輸”,指導學生:何盈杰 旺宏教育基金會
校外榮譽事項 2011 100年度優良晶片,優良設計獎 國家晶片系統設計中心
校外榮譽事項 2008 97年度優良晶片獎,佳作設計獎 ”A 0.8V 3μW Analog Front-End IC for Biomedical Signal Recording”,指導學生:高碩廷 國家晶片系統設計中心
校外榮譽事項 2008 97年度優良晶片,設計佳作獎,”Inductor Less LC Oscillator”,指導學生:呂鴻文、史汝敏、蘇朝琴、劉建男 國家晶片系統設計中心
校外榮譽事項 2006 指導學生任慶霖、潘威翔榮獲教育部 類比電路設計(不分組) 優等 教育部
校外榮譽事項 2006 指導學生楊永祥、程議賢榮獲教育部 類比電路設計(不分組) 佳作 教育部
校外榮譽事項 2006 95年度優良晶片獎,優良設計獎 ”A 10Gbps Tree-Type Multiplexer Design” ,指導學生:呂鴻文、陳冠宇 國家晶片系統設計中心
校外榮譽事項 2005 94年度優良晶片獎,優良設計獎”A 42uW 67dB SNDR Sigma Delta ADC”,指導學生:林柏成 國家晶片系統設計中心
校外榮譽事項 2004 93年度優良晶片獎,特優獎 ”All digital 625Mbpss & 2.5Gbps deskew buffer design”,指導學生:莊英廷 國家晶片系統設計中心
校外榮譽事項 2004 93年度優良晶片獎,佳作設計獎 ”A Self-Calibrate All-Digital 3Gbps SATA Driver Design”,指導學生:王信文 國家晶片系統設計中心
校外榮譽事項 2004 矽導計劃晶片系統國家型科技計畫執行長
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