F.Masuoka, M.Momodomi, Y.Iwata, and R.Shirora, “New Ultra High Density EPROM and Flash EEPROM with NAND Structured Cell,” in IEDM Tech. Dig., pp.552-555, Dec. 1987.
 M.Momodomi, R.Kirisawa, R.Nakayama, S.Aritome, T.Endoh, Y.Itoh, Y.Iwata, H.Oodaira, T.Tanaka, M.Chiba, R.Shirota, and F.Masuoka, “New device technologies for 5V-only 4Mb EE-PROM with NAND structure cell,” in IEDM Tech. Dig., pp.412-415, Dec. 1988.
 R.Shirota, T.Endo, M.Momodomi, R.Nakayama, S.Inoue, R.Kirisawa, and F.Masuoka, “An accurate model of subbreakdown due to Band-to-Band tunneling and its application,” in IEDM Tech. Dig., pp.26-29, Dec. 1988.
 T.Endo, R.Shirota, Y.Tanaka, R.Nakayama, R.Kirisawa, S.Aritome, and F.Masuoka, “New design technology for EEPROM memory cells with 10 million write/erase cycling endurance,” in IEDM Tech. Dig., pp.599-602, Dec. 1989.
 R.Shirota, R.Nakayama, R.Kirisawa, M.Momodomi, K.Sakui, Y.Itoh, S.Aritome, T.Endoh, F.Hatori, and F.Masuoka, "A 2.3 m2 Memory Cell Structure for 16 Mb NAND EEPROM’s," in IEDM Tech. Dig., pp. 103-106, Dec. 1990.
 S.Aritome, R.Shirota, R.Kirisawa, T.Endoh, R.Nakayama, K.Sakui, and F.Masuoka, “A reliable bi-polarity write/erase technology in Flash EEPROMs,” in IEDM Tech. Dig., pp.111-114, Dec. 1990.
 R.Shirota, T.Yamaguchi, “A New Analytical Model for low Voltage Hot Electron Taking Auger Recombination as well as phonon Scattering Process into Account,” in IEDM Tech. Dig. pp.123-126. 1991.
 S.Aritome, S.Satoh, T.Maruyama, H.Watanabe, S.Shuto, G.J.Hemink, R.Shirota, S.Watanabe, and F.Masuoka, "A 0.67m2 Self-Aligned Shallow Trench Isolation Cell (SA-STI-Cell) for 3V-only 256Mbit NAND EEPROM’s," in IEDM Tech. Dig., pp. 61-64, Dec. 1994.
 S.Aritome, Y.Takeuchi, S.Sato, H.Watanabe, K.Shimizu, G.J.Hemink, and R.Shirota, “A novel side-wall transfer-transistor cell (SWATT cell) for multi-level NAND EEPROM’s,” in IEDM Tech. Dig., pp.275-278, Dec. 1995.
 S.Satoh, H.Hagiwara, T.Tanzawa, K.Takeuchi, and R.Shirota, "A Novel Isolation-Scaling Technology for NAND EEPROMs with the Minimized Program Disturbance," in IEDM Tech. Dig., pp. 291-294, Dec. 1997.
 A.Goda, W.Moriyama, H.Hazama, H.Iizuka, K.Shimizu, S.Aritome and R.Shirota, “A Novel Surface-Oxidized Barrier-SiN Cell Technology to improve Endurance and Read-Disturb Characteristics for Gigabit NAND Flash Memories.” In IEDM Tech. Dig., pp.771-774, Dec. 2000.
 F.Arai, S.Satoh, T.Yaegashi, E.Kamiya, Y.Matunaga, Y.Takeuchi, H.Kamata, A.Shimizu, N.Ohtani, N.Kai, S.Takahashi, W.Moriyama, K.Kugimiya, S.Miyazaki, T.Hirose, H.Meguro, K.Hatakeyama, K.Shimizu, R.Shiorta, “High Density(4.4F2) NAND Flash technology Using Super-Shallow Channel Profile(SSCP) engineering.” In IEDM tech. Dig., pp775-778, Dec. 2000.
 Y.Itoh, M.Momodomi, R.Shirota, Y.Iwata, R.Nakayama, R.Kirisawa, T.Tanaka, K.Toita, S.Inoue, and F.Masuoka, “An Experimental 4Mb CMOS EEPROM with a NAND Structured Cell,” in ISSCC Dig. Tech. Papers, pp.134-135, Feb. 1989.
 K.Imamiya, Y.Sugiura, H.Nakamura, T.Himeno, K.Takeuchi, T.Ikehashi, K.Kanda, K.Hosono, R.Shirota, S.Aritome, K.Shimizu, K.Hatakeyama, and K.Sakui, “A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology,” in ISSCC Dig. Tech. Papers, pp.112-113, Feb. 1999.
H.Nakamura, K.Imamiya, T.Himeno, T.Yamamura, T.Ikehashi, K.Takeuchi, M. Kanda, K.Hosono, T.Futatsuyama, K.Kawai, R
N.Arai, F.Arai, K.Hatakeyama, H.Hazama, M.Saito, H.Meguro, K.Conley, K.Quader, Chen.Jian , “A 125mm2 1Gb NAND flash memory with 10MB/s program throughput “ in ISSCC, Dig. Tech. Parers, pp.82-411, Feb. 2002
Ø VLSI technology
 R.Shirota, Y.Itoh, R.Nakayama, M.Momodomi, S.Inoue, R.Kirisawa, Y.Iwata, M.Chiba, and F.Masuoka, “A new NAND cell for ultra high density 5V only EEPROMs,” in Symp. VLSI Technology Dig. Tech. Papers, pp.33-34, June 1988.
 R.Kirisawa, S.Aritome, R.Nakayama, T.Endoh, R.Shirota, and F.Masuoka, "A NAND Structured Cell with a New Programming Technology for High Reliable 5 V-Only Flash EEPROM," in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1990.
 H.Watanabe, S.Aritome, G.J.Hemink, T.Maruyama, R.Shirota, “Sacling of tunnel oxide thickness for Flash EEPROMs Realizing Stress-Induced Leakage Current Reduction”, in Symp. VLSI Technology Dig. Tech. Papers, pp.47-45, June, 1994.
 H.G.Hemink, T.Tanaka, T.Endoh, S.Aritome, and R.Shirota, “Fast and accurate programming method for multilevel NAND flash EEPROM’s,” in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1995.
 S.Satoh, K.Shimizu, T.Tanaka, F.Arai, S.Aritome, and R.Shirota, “A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4Gbit NAND Flash memories,” in Symp. VLSI Technologies Dig. Tech. Papers, pp.108-109, June 1998.
 M.Ichige, Y.Takeuchi, K.Sugimae, A.Sato, M.Matsui, T.Kamigaki, H.Kutsukake, Y.Ishibashi, M.Saito, S.Mori, H.Meguro, S.Miyazaki, T.Miwa, S.Takahashi, T.Iguchi, N.Kawai, S.Tamon, N.Arai, H.Kamata, T.Minami, H.Iizuka, M.Higashitani, T.Pham, G.Hemink, M.Momodomi and R.Shirota, “A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs,” in Symp. VLSI technologies Dig. Tech. Papers, pp.89-90, June 2003.
Ø VLSI Circuits
 T.Tanaka, M.Momodomi, Y.Iwata, Y.Tanaka, H.Oodaira, Y.Itoh, R.Shirota, K.Ohuchi, and F.Masuoka, “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.105-106, June 1990.
 T.Tanaka, Y.Tanaka, H.Nakamura, H.Oodaira, S.Aritome, R.Shirota, and F.Masuoka, “A Quick Intelligent Page-Programming Architecture 3V-Only NAND- EEPROMs,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.20-21, June 1992.
 T.Tanzawa, T.Tanaka, K.Takeuchi, R.Shirota, S.Aritome, H.Watanabe, G.Hemink, K.Shimizu, S.Sato, Y.Takeuchi, and K.Ohuchi, “A compact on-chip ECC for low cost Flash memories,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.59-60, June 1996.
Ø Other Conferences
 M.Momodomi, Y.Iwata, T.Tanaka, Y.Ithoh, R.Shirota, F.Masuoka, “A high density NAND EEPROM with Block-page Programming for Micorcomputer Applications”, in IEEE CICC, pp.10.1.1-4, May, 1989.
 S.Aritome, R.Kirisawa, T.Endoh, N.Nakayama, R.Shirota, K.Sakui, K.Ohuchi, and F.Masuoka, “Extended Data Retention Characteristics after more than 104 Write and Erase Cycles in EEPROM’s,” in IEEE IRPS 1990, pp.259-264, 1990.
 S.Aritome, K.Hatakeyama, T.Endoh, T.Yamaguchi, S.Shuto, H.Iizuka, T.Maruyama, H.Watanabe, G.J.Hemink, T.Tanaka, M.Momodomi, K.Sakui, and R.Shirota, “A 1.13mm2 memory cell technology for reliable 3.3V 64M NAND EEPROMs,” in Extended Abstracts of SSDM, pp.446-448, Aug.1993.
 M.Momodomi, R.Shirota, K.Sakui, T.Endoh, and F.Masuoka, “Trend of NAND Flash memory and future development,” in International Workshop on Advanced LSI’s, pp.219-225, July 1995.
 K.Sakui, T.Tanaka, H.Nakamura, M.Momodomi, T.Endoh, R.Shirota, S.Watanabe, K.Ohuchi, and F.Masuoka, “A shielded bitline sensing technology for a high-density and low-voltage NAND EEPROM design,” in International Workshop on Advanced LSI’s, pp.226-232, July 1995.
 K.Sakui, Y.Itoh, R.Shirota, Y.Iwata, S.Aritome, T.Tanaka, K.Imamiya, J.Kishida, M.Momodomi, and J.Miyamoto, “Invited Paper: NAND Flash memory technology and future direction,” in IEEE 1997 NVSMW, pp.1-34, Feb. 1997.
 F.Arai, T.Maruyama and R.Shirota, “Extended Data Retention Process Tcdhnology for Highly Reliable Flash EEPROMs of 106 to 107 W/E Cycles”, in IEEE IRPS 1998, pp.378-382, April 1998.
 R.Shirota, “Invited paper: A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend.” in Non-Volatile Semiconductor Memory Workshop, pp.22-32, Feb.2000.
 R.Shirota, “Invited paper:Future Trends in NAND-Type Flash Memory,” in Extended Abstracts of SSDM, pp.250-251, Aug.2004.
 R.Shirota, “Review of NAND Flash reliability,” in IEEE IRPS Tutorial notes, No.223, April 2005.
 R.Shirota, “NAND Flash Scaling and Technology Development” in Japan Semiconductor Technology Forum”, Jan. 2006.
 R.Shirota, “ Roadmap of the Flash Memory”, IEEE International Workshop on Digital Object Identifier in Memory Technology, Design, and Testing, MTDT, pp: xii – xii, Jun. 2006
 BREAKTHROUGH---Memory of the Future, The JAPAN, Journal, August, 2006
 R.Shirota, “Scaling trend of Flash memory for File storage”, in Memory, Tech, Design, Testing Workshop, pp.16, 2007.
 R.Shirota, “Review of recent development of high density Flash memory”, in New Non-Volatile Memory Workshop at ITRI, session B1, Nov. 2008.
 Hsin-Heng Wang, Chiu-Tsung Huang, Shin-Hsien Chen, Kuo, R, Sophia Liu, Ling-Kuey Yang, Houng-Chi Wei, Pittikoun, S., R.Shirota
, Chin-chen Cho, ”A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory”, in VLSI-TSA International Symposium, pp.
87 – 88, 2008.
 R.Shirota, “Review of Recent Flash Memory Development”, in Symposium on Nano Device Technology, Session 1.2, Apr. 2010.
 C.H.Liu, Y.M.Lin, R.Shirota, H.C.Wei, L.T.Kuo, C.Han.Liu, S.H.Chen, H.P.Wang, Y.Sakamoto, S.Pittikoun, “Self-Aligned Trench Isolation Recess Effect on Cell Performance and Reliability of 42nm NAND Flash Memory”, in VLSI-TSA, Session 3.1, Apr. 2010.