International Conference/Meeting (Peer Reviewed)
1.1 H. Watanabe, K. Matsuzawa, S. Takagi, “Impact of two-dimensional structure of nMOSFETs on direct tunnel gate current”, Extended abstracts of the 2001, international conference on solid state devices and materials (SSDM), Tokyo, 2001, pp. 142-143
1.2 K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, S. Takagi, “Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5nm”, IEDM Tech. Dig., 2002, pp. 47-50
1.3 H. Watanabe, K. Matsuzawa, S. Takagi, “Importance of exact modeling for degenerated poly-Si of MOSFETs with ultra-thin oxide”, Extended abstracts of the 2002 international conference on solid state devices and materials (SSDM), Nagoya, 2002, pp. 410-411
1.4 H. Watanabe, K. Uchida, A. Kinoshita, “Quantum confinement effect of ultrathin-SOI on double-gate nMOSFETs”, Extended abstracts of the 2003 international conference on solid state devices and materials (SSDM), Tokyo, 2003, pp. 270-271
1.5 H. Watanabe, D. Matsushita, K. Muraoka, “Determination of tunnel mass and thickness of gate oxide including poly-Si/SiO2 and Si/SiO2 interfacial transition layers”, Extended abstracts of the 2004 international conference on solid state devices and materials (SSDM), Tokyo, 2004, pp. 732-733
1.6 H. Watanabe, D. Matsushita, K. Muraoka, “Impact of interfacial transition layers between Si and SiO2 and between poly-Si and SiO2 on electrical characteristics”, The 10-th meeting of gate stack, Mishima, 2005, pp. 243-248
1.7 H. Watanabe, K. Nakajima, K. Matsuo, T. Saito, T. Kobayashi, “Reduction of accumulation thickness in metal gate”, Extended abstracts of the 2005 international conference on solid state devices and materials (SSDM), Kobe, 2005, pp. 504-505
1.8 H. Watanabe, “Statistics of Grain Boundaries in Gate Poly-Si”, Proc. simulation of semiconductor process and devices (SISPAD), 2005, pp. 39-42
1.9 H. Watanabe, D. Matsushita, K. Muraoka, K. Kato, “Leakage mechanism of ultrathin SiON gate dielectric”, Extended abstracts of the 2006 international conference on solid state devices and materials, Yokohama, 2006, pp. 1126-1127
1.10 H. Watanabe, K. Matsuo, T. Kobayashi, K. Nakajima, T. Saito, “Weak accumulation of gate polysilicon”, Proceedings of the 11th international workshop on computational electronics (IWCE-11), Technical University of Vienna, May 25-27, 2006, pp. 89-90
1.11 H. Watanabe, “Hopping transport of electrons via Si-dot”, Proceedings of simulation of semiconductor process and devices (SISPAD). Vol. 12, Edited by T. Grasser and S. Selberherr, 2007, pp. 249-252
1.12 H. Watanabe, “Transient device simulation of trap-assisted leakage in non-volatile memory cell”, SISPAD08, Hakone, September 9, 2008.
1.13 H. Watanabe, K. Kawabata, T. Ichikawa, “Trial application of tight-binding method to Si-cluster in optimized SiO2-network”, SISPAD09, San Diego, September 9-11, 2009.
1.14 C-H. Yu, Ming-Hung Han, H-W. Cheng, Z-C. Su, Y. Li, H. Watanabe, “Statistical Simulation of Metal-Gate Work-Function Fluctuation in Emerging High-K/Metal-Gate CMOS Devices”, SISPAD2010, Bologna, September 6-8, 2010, pp. 153-156.
1.15 (Invited) H. Watanabe, “Quantitative discussion electron-hole universal tunnel mass dielectric oxide-nitride", 11-International Symposium Silicon Nitride, Dioxide, Dielectrics, 219th Meeting Electrochemical Society, Montreal, Canada, May 1 to May 6, 2011.
Invited Talks:
2.1 H. Watanabe, “Hidden order and edge effect in quantum spin-ladder”, Abstracts of the meeting of the Physical society of Japan, Sectional meeting, vol. 1995, No.3 (19950912) pp.205-206, 1995 (in Japanese).
2.2 H. Watanabe, K. Matsuzawa, “New BGN model in device simulation --- Calculation method of non-equilibrium BGN ---”, Abstract of the 48 annual meeting of Japan society of applied physics, Tokyo, 2001, p. 35.
2.3 H. Watanabe, K. Matsuzawa, S. Takagi, “3D device simulation of direct tunneling current -- Gate width dependence of SOI-nMOSFET”, Abstract of the 49 annual meeting of Japan society of applied physics, Kanagawa, 2002, p. 52.
2.4 K. Uchida, H. Watanabe, J. Koga, A. Kinoshita, S. Takagi, “Experimental study on carrier transport mechanism in ultrathin-body SOI MOSFETs”, Proc. simulation of semiconductor process and devices, 2003, pp. 8-13.
2.5 H. Watanabe, “Statistics of grain boundaries in poly-Si of nMOSFETs”, Abstract of the 50 annual meeting of Japan society of applied physics, Kanagawa, 2003, p. 67.
2.6 H. Watanabe, “Depletion approximation of gate poly-Si”, the 51-th annual meeting of Japan society of applied physics, 29p-B-6, Tokyo, 2004.
2.7 H. Watanabe, D. Matsushita, K. Muraoka, “Impact of poly-Si interfacial transition layer on tunnel mass”, The 52-th annual meeting of Japan society of applied physics, 29p-zd-2, Saitama, 2005.
2.8 H. Watanabe, K. Matsuo, T. Kobayashi, T. Saito, K. Nakajima, “Weak accumulation of gate polysilicon”, the 53-th annual meeting of Japan society of applied physics, 22a-ZA-3, Tokyo, 2006.
2.9 H. Watanabe, D. Matsushita, K. Muraoka, K. Kato, “On CV-JN characteristics of ultra-thin SiON dielectric including dangling-bonds”, The 54th annual meeting of Japan society of applied physics, 27-aSQ-2, Kanagawa, 2007.
2.10 H. Watanabe, “Lectures on advanced devices physics – CMOS related topics”, Invitation of Dr. Hiroshi Watanabe to the department of electrical engineering in national Tsing Hua university for the lecture on 11/5(Mon), 2007, from 16:00-19:00 @ Electrical Engineering & Computer Science building 410 room. (Coordinator: Prof. R. Shirota)
2.11 H. Watanabe, “Modeling of relation between atomistic dangling-bond and electrical measurement in gate dielectric”, Dec. 17, 2007, University of Modena, Italy. (Coordinator: Prof. R. Brunetti)
2.12 H. Watanabe, “Modeling of relation between atomistic dangling-bond and electrical measurement in gate dielectric”, Dec. 18, 2007, Politecnico di Milano, Italy. (Coordinator: Prof. D. Ielmini)
2.13 H. Watanabe, “Modeling of relation between atomistic dangling-bond and electrical measurement in gate dielectric”, Dec. 19, 2007, University of Bologna, Italy. (Coordinator: Prof. M. Rudan)
2.14 H. Watanabe, “Single electron device simulation”, The 55-th annual meeting of Japan society of applied physics, March, 2008, Chiba
2.15 H. Watanabe, “Interfacial Transition Layer & Tunnel Mass”, National Taiwan University, June 3, 2008, Taipei, Taiwan (Coordinator: Prof. C. W. Lie)
2.16 H. Watanabe, “Digest of the workshop---On requirement for designing advanced electron devices”, June 4, 2008, Taiwan Semiconductor Manufacturing Company, Ltd (TSMC), Tainan, Taiwan (Coordinator: Dr. L. Tran)
2.17 H. Watanabe, “On requirement for designing advanced electron devices”, 2008 Workshop on recent development of Flash Memory and future trend of 32nm and beyond, June 6, 2008, National Chiao Tung University, Hsinchu, Taiwan (Coordinator: Prof. Y. Li)
2.18 H. Watanabe, “Single-electron general-purpose device simulator”, June 10, 2008, SA307, Dept. Appl. Mathematics, National Chiao Tung University, Hsinchu, Taiwan (Coordinator: Prof. M. C. Lai)
2.19 H. Watanabe, “Interfacial transition layer & tunnel mass”, June 10, 2008, Macronix International Co., LTD (MXIC), Hsinchu, Taiwan. (Coordinator: Dr. K. Hsieh)
2.20 H. Watanabe, “Advanced modeling of single-electron devices”, 101-Th meeting of Silicon Technology Division of Applied Physical Society of Japan, June 11, 2008, Tokyo.
2.21 H. Watanabe, “Numerical study of FG-memory cell with a local trap”, The 56-th annual meeting of Japan society of applied physics, March 30, 2009, Tsukuba
2.22 H. Watanabe, “On scaling impact owing to Si-dot boundary”, Feb. 9, 2010, National Nano-Device Laboratory, Hsinchu, Taiwan
2.23 H. Watanabe, K. Kawabata, T. Ichikawa, “On the electronic states of Si-dot surrounded by silicon-oxide”, The 57-th annual meeting of Japan society of applied physics, March 17, 2010, Tokaidai
2.24 H. Watanabe, “A New Simulation Approach to Development of Electron Devices”, May 26, 2010 at PixArt Inc., Hsinchu, Taiwan, (Coordinator: Dr. Y. H. Yang)
2.25 H. Watanabe, “A quasi-virtual design methodology for advanced- & nano- electron devices”, May 27, 2010 at National Center for High-performance Computing, Hsinchu, Taiwan, (Coordinator: Dr. Weicheng Huang)
2.26 H. Watanabe, “快閃記憶體設計與製造技術特論”, NCTU, July 23-24, 2010.
2.27 H. Watanabe, “On Scaling Impact owing to Si-dot Boundaries”, August 24, 2010, Tech. Univ. Denmark, Copenhagen, Denmark (Coordinator: Prof. M. Brandbyge)
2.28 H. Watanabe, “On Scaling Impact owing to Si-dot Boundaries”, ARCES, U. Bologna, Italy, September 10, 2010 (Coordinator: Prof. M. Rudan)
2.29 H. Watanabe, “Advanced Modeling for FG-NVM cell“, Hynix Semiconductor Inc., Icheon, South Korea, December 23, S. W. Park, CTO, Hynix)
2.30 H. Watanabe, “possibility new interface state of surrounded by oxide§, The Asian Consortium Computational Materials Science Working Group Meeting III ACCMSWGM3) on "Advances in the Nano-device Simulation", Jeju Island, Korea during March 31-April 2, 2011.
Invited Paper
3.1 H. Watanabe, “Haldane gap in S=1/2 quantum spin system: The ground state in a quantum spin ladder”, The Physical Society of Japan (JPS), vol. 49, no. 10, pp. 830-833, 1994.
Conference/Meeting (Others)
4.1 H. Watanabe, K. Nomura, S. Takada, “S=1/2 spin ladder and S=1Haldane phase”, Abstracts of the annual meeting of the Physical society of Japan, Annual meeting, vol. 46, No.3 (19910912) p. 419, 1991.
4.2 H. Watanabe, “A cross-over in the lowest excited state of S=1/2 ladder model”, Meeting of Grants-in-Aid for Scientific Research, Strongly correlated quantum mechanical system, August 13, 1993.
4.3 H. Watanabe, “Energy gap of quantum spin ladder”, Abstracts of the meeting of the Physical society of Japan, Annual meeting, vol. 49, No. 3 (19940316) p. 521, 1994.
4.4 H. Watanabe, “Ground state of quantum spin ladder”, Abstract of the meeting of the Physical society of Japan, Sectional meeting, vol. 1994, No.3 (19940816) p.473, 1994.
4.5 H. Watanabe, S. Takagi, “Impact of incomplete ionization of gate impurity and band-gap narrowing on tunnel gate leak of MOS structure”, Abstract of the 47 annual meeting of Japan society of applied physics, Tokyo, 2000, p. 772
4.6 H. Watanabe, S. Takagi, “Effect of incomplete ionization of gate impurity and band-gap narrowing on tunneling current from the gate”, Technical report of IEICE VLD vol. 100 no. 294(20000915), pp. 57-62, VLD2000-66, 2000.
4.7 H. Watanabe, “Advanced modeling of single-electron devices”, Silicon Nanotechnology, VLD-103, Tokyo, July 11, 2008.
4.8 K. Kawabata, T. Ichikawa, H. Watanabe, “Application of tight-binding calculation to optimized Si-SiO2 cluster”, VLD-116, Nov. 13, 2009.
國立交通大學 電機工程學系