| 2013 |
Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Pei-Yu Hsu, Chien-Ying Yu, Yuhwai Tseng, Tze-Zheng Yang, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee,” A 48.6-to-105.2μW Machine-Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Monitoring,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2013" target='_blank'> Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Pei-Yu Hsu, Chien-Ying Yu, Yuhwai Tseng, Tze-Zheng Yang, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee,” A 48.6-to-105.2μW Machine-Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Monitoring,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2013 |
| 2013 |
Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Shiou-Ming Chuang, Tze-Zheng Yang, Chauchin Su, and Chen-Yi Lee,” A Sub-100uW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Application,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2012, pp. 156-157" target='_blank'>Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Shiou-Ming Chuang, Tze-Zheng Yang, Chauchin Su, and Chen-Yi Lee,” A Sub-100uW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Application,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2012, pp. 156-157 |
| 2013 |
Yingchieh Ho, Yu-Sheng Yang and Chauchin Su, “A 0.2-0.6 V Ring Oscillator Design Using Bootstrap Technique,” in IEEE Asian Solid-State Circuits Conference (ASSCC) Digest of Tech. Papers, Jeju, Nov. 14th-16th, 2011, pp. 333-336.
" target='_blank'>Yingchieh Ho, Yu-Sheng Yang and Chauchin Su, “A 0.2-0.6 V Ring Oscillator Design Using Bootstrap Technique,” in IEEE Asian Solid-State Circuits Conference (ASSCC) Digest of Tech. Papers, Jeju, Nov. 14th-16th, 2011, pp. 333-336.
|
| 2013 |
Tsunhsin Wang, Yingchieh Ho, Yuhwai Tseng, and Chauchin Su, “A Hearing-Aid Front-End Circuit Based on Low Power And Low Area Mix Mode AGC” The 8th IASTED International Conference on Biomedical Engineering Biomed 2011, Feb.16-18, 2011, Innsbruck, Austria.
" target='_blank'>Tsunhsin Wang, Yingchieh Ho, Yuhwai Tseng, and Chauchin Su, “A Hearing-Aid Front-End Circuit Based on Low Power And Low Area Mix Mode AGC” The 8th IASTED International Conference on Biomedical Engineering Biomed 2011, Feb.16-18, 2011, Innsbruck, Austria.
|
| 2011 |
Hung-Wen Lin, Ying-Chieh Ho, YingLin Fa, and ChauChin Su, "A 5Gb/s Pulse Signaling
Interface for Low Power On-Chip Data Communication," International Symposium on
Circuits and Systems, A1-L, pp. 201-204, 2010. |
| 2011 |
Shuo-Ting Kao, Hung-Wen Lu, Chau-Chin Su, “A 1.5V 7.5uW Programmable Gain
Amplifier for Multiple Biomedical Signal Acquisition,” in Proceedings of IEEE
Biomedical Circuits and Systems Conference, November 2009. |
| 2011 |
Wei-Chang Liu, Chih-Hsien Lin, Shyh-Jye Jou, Hung-Wen Lu, Chau-Chin Su, Kai-Wei
Hong, Kuo-Hsing Cheng, Shyue-Wen Yang, Ming-Hwa Sheu, “An illustration of
micro-network on chip with 10-Gb/s transmission links,” in Proceedings of Asia Solid
State Circuit Conference, November 2009. |
| 2011 |
Hungwen Lu, Chauchin Su, and Chien-Nan Liu, ”A Scalable Digitalized Buffer for
Gigabit I/O,” in Proceedings of Custom Integrated Circuits Conference, pp.241-244,
September 2008. |
| 2011 |
Jenchien Hsu; Maohsuan Chou; Chauchin Su, “Built-in jitter measurement methodology
for spread-spectrum clock generators,” in Proceedings IEEE International Symposium on
VLSI Design, Automation and Test, 2008, pp.67-72. |
| 2011 |
H.K. Chen and Chauchin Su, “A test and diagnosis methodology for RF transceiver,” IEEE
2007 Asian Test Symposium, Oct. 2007. |
| 2011 |
ChauChin Su, Po-Chen Lin, and HungWen Lu, “ An Inverter Based 2-MHz 42-uW delta
sigma ADC with 20-KHz Bandwidth and 66dB Dynamic Range,” Asia Solid State Circuit
Conference, Nov. 2006 |
| 2011 |
Maohsuan Chou, JenChien Hsu and Chauchin Su, “A Digital BIST Methodology for Spread
Spectrum Clock Generators” The Fifteenth Asian Test Symposium, Nov. 2006 |
| 2011 |
JenChien Hsu and Chauchin Su, “BIST for Jitter Measurement and Jitter Decomposition of
CDR,” IEEE International Mixed-Signals Testing Workshop, Jun. 2006. |
| 2011 |
S.M. Li, Y.W. Chang, C.C. Su, C.L. Lee, J.E. Chen, “IEEE Std. 1500 Compatible
Interconnect Diagnosis for Delay and Crosstalk Faults,” Proc. 2005 ASPDAC, pp.366-371. |
| 2011 |
Hsin Wen Wang, Hung Wen Lu, ChauChin Su, ”A Self-Calibrate All-Digital 3Gbps SATA
Driver Design” Proc. Asia Solid State Circuit Conference (ASSCC), Nov 2005, pp. 57-60. |
| 2011 |
Hung Wen Lu, ChauChin Su, ” A 1.25 to 5Gbps LVDS Transmitter with a Novel
Multi-Phase Tree-Type Multiplexer” Proc. Asia Solid State Circuit Conference (ASSCC),
Nov 2005, pp. 389-392. |
| 2011 |
Hung Wen Lu, Yin Tin Chang, ChauChin Su, "All digital 625Mbps & 2.5Gbps deskew
buffer design," Proc. VLSI Design, Automation and Test (VLSI-TSA-DAT), April 2005,
pp.263–266. |
| 2011 |
Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su “A Spread Spectrum Clock
Generator for SATA-II,” Proc. International Symposium on Circuit and System
(ISCAS),May 2005 |
| 2011 |
JenChien Hsu and Chauchin Su, “BIST for Clock Jitter Measurement of Charge-Pump
Phase-Locked Loops,” Int’l Mixed Signal Test Workshop, 2005. |
| 2011 |
K. S.M. Li, C.L. Lee, C.C. Su, J.E. Chen, “Oscillation Ring Based Interconnect Test Scheme
for SoC,” Proc. 2005 ASPDAC, pp. 184-187. |
| 2011 |
S.M. Li, C.L. Lee, T.Q. Jiang, C.C. Su, J.E. Chen, “Finite State Machine Synthesis for
At-Speed Oscillation Testability,” Proc. 2005 Asian Test Symposium, pp. 360-365. |
| 2011 |
S.M.Li, C.L. Lee, Y.W. Chang, C.C. Su, J.E. Chen, “Multi-Level Routing With Testability
and Yield Enhancement,” Proc. 2005 Int’l Workshop on System Level Design. |
| 2011 |
H.W. Lu and C.C. Su, “A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type
Multiplexer,”Proc. 2004 IEEE Asia-Pacific Conference on Advanced System Integrated
Circuits (AP-ASIC), pp. 228-231. |
| 2011 |
H.W. Wang, H.W. Lu, and C.C. Su, “A Digitized LVDS Driver with Simultaneous
Switching Noise Rejection,” Proc. 2004 IEEE Asia-Pacific Conference on Advanced System
Integrated Circuits (AP-ASIC), pp. 240-243. |
| 2011 |
C.C. Su, C.S. Chang, H.W. Huang, D.S. Tu, C.L. Lee, and J. CH. Lin,“Dynamic Analog
Testing via ATE Digital test Channels, ” Proc. 2004 IEEE Asian Test Symposium, pp.
308-312. |
| 2011 |
K. SM. Li, C.L. Lee, C.C. Su, and J.E. Chen, “A Unified Approach to Detecting Crosstalk
Faults of Interconnected in Deep Submicron VLSI,”Proc. 2004 IEEE Asian Test Symposium,
pp. 145-150. |
| 2011 |
H.K. Chen and C.C. Su,“A Deconvolution Based RF Test Methodology,”2004 IEEE
International Mixed Signal Test Workshop. |
| 2011 |
Chauchin Su; Chih-Hu Wang; Wei-Juo Wang; Tseng, I.S.; "1149.4 based on-line quiescent
state monitoring technique," Proc. IEEE 2003 VLSI Test Symposium (VTS 2003). May
2003, pp. 197 -202. |
| 2011 |
Shi-Dai Mai; Lune, H.; Ren-Chien Hsu; Chauchin Su; "An autonomous multiple module
clock synchronization methodology for SoC," Proc. IEEE 2003 International System on
Chip Conference (SoC 2003), Sept. 2003, pp. 39 -42. |
| 2011 |
Chauchin Su; Wei-Juo Wang; Chih-Hu Wang; Tseng Is; "A novel LCD driver testing
technique using logic test channels," Proc. 2003 Asia and South Pacific (ASP-DAC 2003),
Jan. 2003, pp. 657 -662. (Invited) |
| 2011 |
Wenliang Tseng; Sonfu Yeh; Pojen Huang; Chauchin Su; "Qualitative analysis of coupled
transmission lines," Proc. 2003 Electronic Components and Technology Conference (ECTC
2003), May 2003, pp. 1656 -1663. |
| 2011 |
Wenliang Tseng; Pojen Huang; Sonfu Yeh; Chauchin Su; "Equivalent circuits for the
qualitative analysis of the transmission line reflection effects," Proc. 2002 Electrical
Performance of Electronic Packaging Conference (EPEP 2002), Oct. 2002, pp. 145 -148. |
| 2011 |
C.C. Su and W.L Tzeng, "Configuration Free SoC Interconnect BIST Methodology," Proc.
2001 Int'l Test Conference (ITC 2001), Baltimore, Maryland, Oct. 2001 (to appear). |
| 2011 |
Y.T. Chen and C.C. Su, "Test Waveform Shaping in Mixed Signal Test Bus by
Pre-Equalization," Proc. 2001 VLSI Test Symposium (VTS 2001), Marina Beach, Los
Angles, U.S.A. pp.260-265. |
| 2011 |
C.C. Su, et. al., "A Computer Aided Engineering System for Memory BIST," Proc. 2001
Asia and South Pacific Design Automation Conference, 2001. |
| 2011 |
C.C. Su, et. al., "A Computer Aided Engineering System for Memory BIST," Proc. 2001
Asia and South Pacific Design Automation Conference, 2001. |
| 2011 |
J.W. Lin, C.L. Lee, C.C. Su, and J.E. Chen, "Fault Diagnosis for Linear Analog Circuits,"
Proc. 9th Asian Test Symposium, 2000, pp. 25-30. |
| 2011 |
Y.C. Huang, C.L. Lee, J.W. Lin, J.E. Chen and C.C. Su, "A Methodology for Fault Model
Development for Hierarchical Linear Systems," Proc. 9th Asian Test Symposium, 2000, pp.
90-95. |
| 2011 |
C.W. Lu, C.L. Lee, C.C. Su, and J.E. Chen, "Is IDDQ Testing Not Applicable for Deep
Submicron VLSI in Year 2011?" Proc. 9th Asian Test Symposium, 2000, pp. 338-343. |
| 2011 |
C.W. Lu, C.L. Lee, C.C. Su, and J.E. Chen, "Is IDDQ Testing Not Applicable for Deep
Submicron VLSI in Year 2011?" Proc. 9th Asian Test Symposium, 2000, pp. 338-343. |
| 2011 |
C.C. Su, et. al., "A Distributed At-Speed TDBI Memory Test System", Proc. 2000 Test
Resource Partitioning Workshop, Oct. 2000. |
| 2011 |
C.C. Su, Y.T. Chen, M.J. Huang, G.N. Chen, and C.L. Lee, “All Digital Built-in Delay and
Crosstalk Measurement for On-Chip Buses,” Proc. 2000 IEEE Design, Automation and Test
in Europe (DATE 2000), Paris, France, March 2000. |
| 2011 |
Y.T. Chen and C.C. Su, “Crosstalk Effect Removal for Analog Measurement in Analog Test
Bus”, Proc. 2000 IEEE VLSI Test Symposium (VTS 2000), Montreal, Canada, May 2000. |
| 2011 |
C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
Environment,” 1999 Asian Test Symposium, Nov. 1999, pp. 233-239. |
| 2011 |
C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
Environment,” 1999 Asian Test Symposium, Nov. 1999, pp. 233-239. |
| 2011 |
C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
Environment,” 1999 Asian Test Symposium, Nov. 1999, pp. 233-239. |
| 2011 |
C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
Environment,” 1999 Asian Test Symposium, Nov. 1999, pp. 233-239. |
| 2011 |
C.C. Su, L.Y. Huang, J.J. Lee, and C.K. Wang, “A Frame-Based Symbol Timing Recovery
for Large Pull-in Rang and Small Steady Sate Variation,” Proc. 1999 Asia Pacific
Conference on ASICs, 1999, pp. 75-78. |
| 2011 |
C.C. Su, “A Linear Optimal Test Generation Algorithm for Interconnect Testing,” Proc.
1998 IEEE Int’l Conference on Computer Aided Design, 1998, pp. 290-295 |
| 2011 |
C.C. Su, S.J. Jeng, and Y.T. Chen, “Boundary Scan BIST Methodology for Reconfigurable
Systems,” Proc. 1998 IEEE Int’l Test Conference, 1998 774-783. |
| 2011 |
Y.T. Chen and C.C. Su, “Analog Module Metrology Using MNABST-1 P1149.4 Test
Chip,” Proc. IEEE Asian Test Symposium, 1998 378-382. |
| 2011 |
C.C. Su, “Comprehensive Interconnect BIST Methodology for Virtual Socket Interface,”
Proc. IEEE Asian Test Symposium, 1998, pp.259-263. |
| 2011 |
Chih-Wen Lu; Chung Len Lee; Chen, J.E.; Chauchin Su; "A new IDDQ testing scheme
employing charge storage BICS circuit for deep submicron CMOS ULSI," Proc. 1998
International Workshop on IDDQ Testing, November 1998, pp. 54 -58. |
| 2011 |
C.C. Su, Y.T. Chen, and S.J. Jou, ``Parasitic Effect Removal for Analog Measurement in
P1149.4 Environment," Proc. 1997 IEEE Int'l Test Conference, 1997. |
| 2011 |
C.C. Su, Y.R. Cheng, Y.T. Chen, and S. T, ``Analog Signal Metrology for Mixed Signal
ICs," Proc. 1997 IEEE Asia Test Symposium, 1997. |
| 2011 |
C.C. Su, Hung-Chi Lin, and Shye-Jye Jou, ``Mixed Signal Design of Cascadable Matched
Filters," Proc. 1997 IEEE Int'l Symp. on Circuits and Systems, 1997. |
| 2011 |
C.C. Su, Chenq-Fan Yen, and Jang-Chuang Yo, ``Hardware Efficient Updating Technique
for LZW CODEC Design," Proc. 1997 IEEE Int'l Symp. on Circuits and Systems, 1997. |
| 2011 |
C.C. Su, K.Y. Chen, and S.J. Jou, ``Structural Approach for Performance Driven ECC
Circuit Synthesis," Proc. 1997 Asian and South Pacific Design Automation Conference,
1997. |
| 2011 |
C.C. Su, Yue-Tsang Chen, Shyh-Jye Jou, and Yuan-Tzu Ting, ``Metrology for Analog
Module Testing Using Analog Testability Bus," Proc. 1996 Int'l Conf. on Computer Aided
Design, 1996. |
| 2011 |
C.C. Su, Shyh-Shen Hwang, Shyh-Jye Jou, and Yuan-Tzu Ting, ``Syndrome Simulation and
Syndrome Test for Unscanned Interconnects," Proc. 1996 Asian Test Symposium, 1996. |
| 2011 |
C.C. Su, S.J. Jou, and Y.T. Ting, ``Decentralized BIST for 1149.1 and 1149.5 Based
Interconnects," Proc. 1996 European Design and Test Conference, pp. 120-125 1996. |
| 2011 |
S.C. Yin, C.C. Su, et.al., ``A New VSB Modulation Technique and Shaping Filter Design,"
Proc. 1996 Int'l Symp. on Circuits and Systems, 1996. |
| 2011 |
C.C. Su, S.S. Chiang, S.J. Jou, ``Impulse Response Fault Model and Fault Extraction for
Functional Level Analog Circuit Diagnosis," Proc. Int'l Conference on Computer Aided
Design, San Jose CA USA, pp.631-636. 1995. |
| 2011 |
C.C. Su, S.S. Chiang, S.J. Jou, ``Impulse Response Fault Model and Fault Extraction for
Functional Level Analog Circuit Diagnosis," Proc. Int'l Conference on Computer Aided
Design, San Jose CA USA, pp.631-636. 1995. |
| 2011 |
Shyh-Jye Jou; Kou-Fong Liu; Chauchin Su; "Circuits design optimization using symbolic
approach," Proc. IEEE 1995 International Symposium on Circuits and Systems, April 1995,
pp. 1396 -1399 vol.2. |
| 2011 |
C.C. Su, K.C. Hwang, and S.J. Jou, ``An IDDQ Based Built-in Concurrent Test Technique
for Interconnects in a Boundary Scan Environment," Proc. IEEE Int'l Test Conference,
Washington DC USA, Oct. 1994, pp.670-676. |
| 2011 |
C.C. Su, ``Random Testing Methodologyof Interconnects in a Boundary Scan Environment,"
Proc. 1994 European Design and Test Conference, Paris France, Feb. 1994, pp. 226-231. |
| 2011 |
C.C. Su, and K.C. Hwang, ``A Serial Scan Test Vector Compression Mthodology," Proc.
IEEE Int'l Test Conference, Baltimore MD USA, Oct. 1993, pp.981-988. |
| 2011 |
C.Y. Chang and C.C. Su, ``An Universal BIST Methodology for Interconnects," Proc. IEEE
Int'l Symp. on Circuits and Systems, Chicago IL USA, May 1993, pp.1615-1618. |
| 2011 |
60. C.C. Su and J.H. Wang, ``A Synthesis Tool for ECC Circuits," Proc. IEEE Int'l Symp. on
Circuits and Systems, Chicago IL USA, May 1993, pp.1706-1709. |
| 2011 |
C.C. Su}, et. al., ``A BIST Methodology for Iterative Logic Arrays," Proc. IEEE Int'l Symp.
on Circuits and Systems, San Diego, CA USA, May 1992, pp.411-414. |
| 2011 |
S.J. Jou, C.Y. Chen, E.C. Yang, and C.C. Su, ``A Pipelining Multiplier Accumulator Using
a High Speed Low Power Static and Dynamic Full Adder Design," IEEE Custom Integrated
Circuits Conference, May 1995, pp. 27.6.1-27.6.4. |
| 2011 |
W.H. Shieh, S.J. Jou, and C.C. Su, ``A Parallel Even-Driven MOS Timing Simulator for
Distributed Memory Multiprocessor," Proc. Int'l Symp. on Circuits and Systems, Seatle
USA, May, 1995, pp. 139-1399. |
| 2011 |
S.J. Jou, K.F. Liu, and C.C. Su, ``Circuit Design Optimization Using Symbolic Approach,"
IEEE Int'l Symp. Circuits and Systems, Seatle USA, May 1996, pp. 574-577. |
| 2011 |
S.J. Jou, M.F. Perng, C.C. Su, and C.K. Wang, ``Hierarchical Techniques for Symbolic
Analysis of Large Electronic Circuits," Proc. Int'l Symp. on Circuits and Systems, Landon,
U.K., May, 1994. |
| 2011 |
Chou-Ming Kuo, Ying-Chieh Ho and Chauchin Su, ” A 4-bit 5-GSample/s Low-Power
Digitalized A/D Converter for Pulse Amplitude Modulation System,” 21th VLSI Design and
CAD Symposium, Aug. 2010. |
| 2011 |
Ya-Ting Chen, Ying-Chieh Ho and Chauchin Su, ” A Power Efficient On-chip Bus Design
with Dynamic Voltage and Frequency Scaling Scheme,” 20th VLSI Design and CAD
Symposium, Aug. 2009. |
| 2011 |
H.W. Lu, C.C. Yang, J.M. Shih and C.C. Su, " A 10Gb/s/pin Transceiver for On-Chip Bus
with All-Digital SerDes Scheme," 20th VLSI Design and CAD Symposium, Aug. 2009. |
| 2011 |
H.W. Lu, J.M. Shih and C.C. Su, " All-Digital Resonant DCO with Inverter-based Tunable
Active Inductor," 20th VLSI Design and CAD Symposium, Aug. 2009. |
| 2011 |
S.-T. Kao, H.W. Lu, S.M. Chuang and C.C. Su, " A Low Power Analog Front-End for
Biomedical Signal Recording," 20th VLSI Design and CAD Symposium, Aug. 2009. |
| 2011 |
S.-T. Kao, H.W. Lu, S.M. Chuang and C.C. Su, " A 1.5-V Programmable Front-End
Bio-Potential Signal Acquisition IC," 20th VLSI Design and CAD Symposium, Aug. 2009. |
| 2011 |
JenChien Hsu and Chauchin Su,“BIST for Measuring Signal Eye Opening in High Speed
I/O”, 19th VLSI Design and CAD Symposium, Aug. 2008. |
| 2011 |
H.W. Lu and C.C. Su, "A Scalable Digitalized Buffer for Gigabit I/O," 19th VLSI Design
and CAD Symposium, Aug. 2008. |
| 2011 |
H.W. Lu, KuanYu Chen, Chau-Chin Su, “A Low Power Tree-Type Multiplexer with
embedded timing skew switch, ” 18th VLSI Design and CAD Symposium, Aug. 2007. |
| 2011 |
H.W. Lu, KuanYu Chen, Chau-Chin Su, “A Digitalize LVDS Driver with Output Level
Self-Calibrate and Pre-Emphasis,” 17th VLSI Design and CAD Symposium, Aug. 2006. |
| 2011 |
H.W. Lu and C.C. Su, “A 2.5Gbps Digitalize LVDS Transceiver design,” 15th VLSI Design
and CAD Symposium, Aug. 2004. |
| 2011 |
H.W. Wang, H.W. Lu and C.C. Su, “A Digitized LVDS Driver with Simultaneous
Switching Noise Rejection, ” 15th VLSI Design and CAD Symposium, Aug. 2004. |
| 2011 |
H.W. Lune and C.C. Su, "A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type
Multiplexer," Proc. 14th VLSI Design and CAD Symposium, Aug. 2003, pp. 62-65. |
| 2011 |
W.L Tseng, S.F, Yeh, P. H. Huang, and C. C. Su, "Qualitative Analysis of N-Coupled
Transmission Lines," Proc. 14th VLSI Design and CAD Symposium, Aug. 2003, pp.
289-292. |
| 2011 |
W.L Tseng, S.F. Yeh, P.J, Huang, and C.C. Su, "Literal Reflection Effect Equivalent
Circuits of Transmission Line Analysis," Proc. 13th VLSI Design and CAD Symposium,
Aug. 2002, pp. 293-296. |
| 2011 |
C.C. Su, C.H. Lin, and C.L. Hu, "A Sigma-Delta Modulation Based Carrier Recovery
Architecture for the ATSC HDTV," Proc. 11th VLSI Design/CAD Symposium, Aug. 2000,
pp.293-296. |
| 2011 |
C.C. Su, G.N Chen, and Y.T. Chen, "A Design for Diagnosis Technique for the Delay and
Crosstalk Measurement of On-Chip Bus Wires," Proc. 11th VLSI Design/CAD Symposium,
Aug. 2000, pp.293-296. |
| 2011 |
Y.C. Huang, C.L, Lee, J.E. Chen, and C.C. Su, “Hierarchical Fault Model,” Proc. 10th VLSI
Design/CAD Symposium, Aug. 1999, pp. 199-202 |
| 2011 |
Y.T. Chen and C.C. Su, “Parasitic Effect Removal for Analog Measurement in MNABST-1
P1149.4 Test Chip Environment,” Proc. 9th VLSI Design/CAD Symposium, Aug. 1998,
pp.181-184. |
| 2011 |
J.S. Liu, Y.H. Jaeng, and C.C. Su, “Code Tracking Loop for the Synchronization of IS-95
CDMA,” Proc. 9th VLSI Design/CAD Symposium, Aug. 1998, pp.219-222. |
| 2011 |
S.J. Kuo, C.L. Lee, J.E. Chen, and C.C. Su, “A Fault Diagnosis Technique for Delta-Sigma
Analog to Digital Converters,” Proc. 9th VLSI Design/CAD Symposium, Aug. 1998,
pp.133-136. |
| 2011 |
C.C. Su and Y.T. Chen ``BIST Methodology for Comprehensive Interconnect Testing,”
Proc. 8th VLSI Design/CAD Symposium, Aug. 1997, pp.73-76. |
| 2011 |
C.C. Su, Y.R. Cheng, Y.T. Chen, and S. Tenchen, ``Analog Signal Metrology by on-chip
ADCs of Mixed Signal ICs,” Proc. 8th VLSI Design/CAD Symposium Aug. 1997,
pp.185-188. |
| 2011 |
S.T. Yin, C.C. Su, M.T. Shieu, C.K. Wang, and W.I. Way, ``A New VSB Modulation
Techniques and Shaping Filter Design," Proc. 6th VLSI Design /CAD Symposium, Chia-Yi
Taiwan ROC, Aug. 1995, pp.120-123. |
| 2011 |
Shieh, S.J. Jou, and C.C. Su, ``Network Hopping Technique for Simulation Tools," Proc.
6th VLSI Design /CAD Symposium, Chia-Yi Taiwan ROC, Aug. 1995, pp.302-305. |
| 2011 |
Jou, C.Y. Chen, and C.C. Su, ``Implementation of High Performance
Multiplier/Accumulator," Proc. 6th VLSI Design /CAD Symposium, Chia-Yi Taiwan ROC,
Aug. 1995, pp.155-160. |
| 2011 |
Lin, C.C. Su, C.K. Wang, and S.J. Jou, ``MixCAD - A Behavioral Level Mixed Mode
System Simulator," Proc. 5th VLSI Design /CAD Symposium, Tainan Taiwan ROC, Aug.
1994, pp.269-274. |
| 2011 |
Jou, C.Y. Chen, C.C. Su, and C.K. Wang, ``Implementation of High Performance
Multiplier/Accumulator," Proc. 5th VLSI Design /CAD Symposium, Tainan Taiwan ROC,
Aug. 1994, pp.155-160. |
| 2011 |
Hsieh, S.J. Jou, and C.C. Su, ``PMOTA - A Parallel Event-Driven MOS Timing Simulator
for Distributed Memory Multiprocessors," Proc. 5th VLSI Design /CAD Symposium, Tainan
Taiwan ROC, Aug. 1994, pp.299-303. |
| 2011 |
Jou, H.F. Liu, and C.C. Su, ``Integrated Circuits Design Optimization Using Symoblic
Approach," Proc. 5th VLSI Design/CAD Symposium, Tainan Taiwan ROC, Aug. 1994,
pp.310-314. |
国立阳明交通大学 电机工程学系